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    Data buffering method used when performing read operation on optical storage medium
    122.
    发明授权
    Data buffering method used when performing read operation on optical storage medium 有权
    在光存储介质上执行读取操作时使用的数据缓冲方法

    公开(公告)号：US07791990B2

    公开(公告)日：2010-09-07

    申请号：US11532102

    申请日：2006-09-15

    Applicant: Jia-Horng Shieh ,  Jin-Bin Yang

    Inventor： Jia-Horng Shieh ,  Jin-Bin Yang

    IPC: G11B5/09

    CPC classification number: G11B20/10527 ,  G11B27/105 ,  G11B2020/10694

    Abstract: A data buffering method used when performing a read operation on an optical storage medium is disclosed. After a first data unit having an unidentifiable and temporarily undeducible ID address is reproduced through the read operation, the method starts storing the first data unit and subsequently reproduced data units into a buffer memory in turn. After a second ID address of a second data unit of the subsequently reproduced data units is identified, the method deduces a target memory address of the buffer memory according to the second ID address and a target ID address. A buffer start pointer is then set according to the deduced target memory address.

    Abstract translation: 公开了一种在光学存储介质上执行读取操作时使用的数据缓冲方法。 在通过读取操作再现具有不可识别且暂时不可消除的ID地址的第一数据单元之后，该方法开始依次将第一数据单元和随后的再现数据单元存储到缓冲存储器中。 在识别出随后再现的数据单元的第二数据单元的第二ID地址之后，该方法根据第二ID地址和目标ID地址推断缓冲存储器的目标存储器地址。 然后根据推导的目标存储器地址设置缓冲区起始指针。

    Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions
    128.
    发明授权
    Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions 有权
    制造具有外延生长的应力诱导源极和漏极区域的MOS器件的方法

    公开(公告)号：US07670934B1

    公开(公告)日：2010-03-02

    申请号：US12359764

    申请日：2009-01-26

    Applicant: Rohit Pal ,  Frank Bin Yang

    Inventor： Rohit Pal ,  Frank Bin Yang

    IPC: H01L21/20 ,  H01L21/36

    CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

    Abstract: Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.

    Abstract translation: 提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准 第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料 第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

    TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD
    130.
    发明申请
    TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD 有权
    具有非对称嵌入式应变元件的晶体管器件及相关制造方法

    公开(公告)号：US20100012975A1

    公开(公告)日：2010-01-21

    申请号：US12176835

    申请日：2008-07-21

    Applicant: Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

    Inventor： Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

    IPC: H01L29/778 ,  H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

    Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

    Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

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