公开(公告)号：US10031754B2

公开(公告)日：2018-07-24

申请号：US14267298

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

公开(公告)号：US20180176191A1

公开(公告)日：2018-06-21

申请号：US15860652

申请日：2018-01-02

Applicant: Netronome Systems, Inc.

Inventor： Roelof Nico du Toit

IPC: H04L29/06

CPC classification number: H04L63/0428 ,  H04L63/168

Abstract: A network device receives TCP segments of a flow via a first SSL session and transmits TCP segments via a second SSL session. Once a TCP segment has been transmitted, the TCP payload need no longer be stored on the network device. Substantial memory resources are conserved, because the device may have to handle many retransmit TCP segments at a given time. If the device receives a retransmit segment, then the device regenerates the retransmit segment to be transmitted. A data structure of entries is stored, with each entry including a decrypt state and an encrypt state for an associated SSL byte position. The device uses the decrypt state to initialize a decrypt engine, decrypts an SSL payload of the retransmit TCP segment received, uses the encrypt state to initialize an encrypt engine, re-encrypts the SSL payload, and then incorporates the re-encrypted SSL payload into the regenerated retransmit TCP segment.

公开(公告)号：US09912533B1

公开(公告)日：2018-03-06

申请号：US14731370

申请日：2015-06-04

Applicant: Netronome Systems, Inc.

Inventor： Brenda Prigg ,  Michael Sobczak ,  Robert Charles Drummond

IPC: H04L12/24 ,  H04L12/26

CPC classification number: H04L41/0823 ,  H04B10/00 ,  H04L1/00 ,  H04L43/0847 ,  H04L43/16 ,  H04L43/50

Abstract: An individual score is generated for a first combination of a transmitter configuration value and a receiver configuration value. The transmitter configuration is used to configure a first physical layer circuit and the receiver configuration is used to configure a second physical layer circuit. The individual score is based on measured characteristics observed by the second physical layer circuit in response to the first configuration combination. A neighbor weighted score is then generated for the first configuration combination. The neighbor weighted score is based on measured characteristics observed by the second physical layer circuit in response to a second configuration combination that is within a first distance from the first configuration combination within a multidimensional array of configuration combinations. The individual score is summed with the neighbor weighted score to generate a final neighbor weighted score for the first configuration combination.

公开(公告)号：US09891985B1

公开(公告)日：2018-02-13

申请号：US14929275

申请日：2015-10-31

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb ,  Benjamin D. Findlen

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  H03M13/096

Abstract: A parser and checksum circuit includes a 256-bit data bus, IPV4, IPV6, TCP, and UDP state signal buses, a checksum summer and compare circuit, four 64-bit parsing circuits, a V6 extension processor, and a parse state context circuit. Each of the 64-bit parsing circuits includes two 32-bit parsing circuits. The data bus receives a data signal that is part of a packet. IPV4, IPV6, TCP, and UDP state signals are each configurable into 1-hot states where at most 1-bit is digital logic high. Each of the 1-hot states corresponds to a segment of a packet header of one of the IPV4, IPV6, TCP, and UDP protocols. Each 32-bit parsing circuit receives a 1-bit shifted version of the state signals received by the adjacent 32-bit parsing circuit and receives a portion of the data signal. State signals and the data signal portion are received in parallel during a single clock cycle.

公开(公告)号：US09753725B2

公开(公告)日：2017-09-05

申请号：US14448906

申请日：2014-07-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

CPC classification number: G06F9/3001 ,  G06F9/30069 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3895 ,  H04L9/0643 ,  H04L2209/125

Abstract: A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo-2 multiplier, a first modulo-2 summer, a modulor-2 divider, and a second modulo-2 summer. The nonlinearizing function circuit receives a hash value from the hash register and performs a programmable nonlinearizing function, thereby generating a modified version of the hash value. In one example, the nonlinearizing function circuit includes a plurality of separately enableable S-box circuits. The multiplier multiplies the input data by a programmable multiplier value, thereby generating a product value. The first summer sums a first portion of the product value with the modified hash value. The divider divides the resulting sum by a fixed divisor value, thereby generating a remainder value. The second summer sums the remainder value and the second portion of the input data, thereby generating a hash result.

公开(公告)号：US09729353B2

公开(公告)日：2017-08-08

申请号：US14151666

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F17/30 ,  G11C15/00 ,  G06F9/44 ,  H04L12/64 ,  G06N5/02

CPC classification number: H04L12/6418 ,  G06F9/4498 ,  G06F17/30283 ,  G11C15/00

Abstract: An NFA hardware engine includes a pipeline and a controller. The pipeline includes a plurality of stages, where one of the stages includes a transition table. Both a first automaton and a second automaton are encoded in the same transition table. The controller receives NFA engine commands onto the NFA engine and controls the pipeline in response to the NFA engine commands.

公开(公告)号：US20170192926A1

公开(公告)日：2017-07-06

申请号：US15463857

申请日：2017-03-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4068 ,  G06F13/14 ,  G06F13/36 ,  G06F13/4022 ,  G06F17/5068

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

公开(公告)号：US09678866B1

公开(公告)日：2017-06-13

申请号：US14724827

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F12/06

CPC classification number: G06F12/063 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/3836 ,  G06F9/467 ,  G06F2212/251 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

公开(公告)号：US09678738B1

公开(公告)日：2017-06-13

申请号：US14671951

申请日：2015-03-27

Applicant: Netronome Systems, Inc.

Inventor： Roelof Nico du Toit ,  Noah Zev Robbin ,  Jason Scott McMullan

IPC: G06F9/445 ,  H04L29/08

CPC classification number: G06F8/65 ,  H04L67/1095 ,  H04L67/1097

Abstract: Software update information is communicated to a network appliance either across a network or from a local memory device. The software update information includes kernel data, application data, or indicator data. The network appliance includes a first storage device, a second storage device, an operating memory, a central processing unit (CPU), and a network adapter. First and second storage devices are persistent storage devices. In a first example, both kernel data and application data are updated in the network appliance in response to receiving the software update information. In a second example, only the kernel data is updated in the network appliance in response to receiving the software update information. In a third example, only the application data is updated in the network appliance in response to receiving the software update information. Indicator data included in the software update information determines the data to be updated in the network appliance.

公开(公告)号：US09665519B2

公开(公告)日：2017-05-30

申请号：US14591003

申请日：2015-01-07

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a “Return Available PPI Credits” command from a credit-aware (CA) device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the CA device, and zeroes out its stored CTBR value. The CA device adds the credits returned to a “Credits Available” value it maintains. The CA device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another aspect, the CA device issues one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.