Abstract:
A portable terminal capable of invoking programs by a sign command and a program invoking method therefore. In the portable terminal, a storage stores programs and symbols linked to the programs. A display displays the operation state of a program when the program is invoked. A user interface senses an external contact and informs a controller that detects a figure represented by a signal sensed at the user interface according to a path in which the external contact is made and, in the presence of a symbol matching the figure, invokes a program corresponding to the symbol from the storage.
Abstract:
A high voltage semiconductor device including a semiconductor substrate on which a semi-insulating polycrystalline silicon layer is formed to alleviate electric field concentration in a field region, is disclosed. A thermal oxide layer is formed on the semi-insulating polycrystalline silicon layer to serve as a protective layer. The thermal oxide layer forms a good interface with the semi-insulating polycrystalline silicon layer compared to a wet etched oxide layer or a chemical vapor deposition (CVD) oxide layer, thereby decreasing the amount of leakage current. In addition, compared to a dual semi-insulating polycrystalline silicon layer, the thermal oxide layer exhibits a high surface protection effect and a high resistance against dielectric breakdown. It also allows a great reduction in fabrication time. In particular, the semi-insulating polycrystalline silicon layer is removed from the active region, thereby preventing the direct current (DC) gain of a device from being lowered within a low collector current range caused by the semi-insulating polycrystalline silicon layer.
Abstract:
An insulated gate bipolar transistor (IGBT) and a method for manufacturing the same is provided. This method is capable of preventing a latch-up and improving a short current characteristic. In the IGBT, a second conductive type semiconductor layer is formed over a semiconductor substrate. A first conductive type well is then formed beneath the surface of the semiconductor layer, and a second conductive type source region doped with a high concentration is formed in the well. Also, a gate electrode is formed over the semiconductor layer, but so as not to contact the source region in a region in which a contact between the source region and a cathode electrode is formed. Also, the IGBT further includes an impurity region for controlling latch-up, the impurity region being extended to a part of the semiconductor layer via the well.
Abstract:
A process for nondestructive heating and supplying of ammonia feed gas wherein high quality ammonia (typically greater than 90% and as high as 99%) is preserved at temperatures well in excess of the conventional limit of 230° C. (typically from 400 to 700° C.) by controlling the selection of metal surfaces in contact with the hot gas, the bulk temperature of the gas, the wall temperature, the pressure, the contact time, and the spatial surface density. Such hot gases are particularly useful for the manufacture of hydrogen cyanide.
Abstract:
A circuit for a clamping an /RAS signal in a DRAM. The bit line pre-charge generator is activated after the set-up of the VBB voltage, so that /RAS signals may be supplied to the chip after the bit line pre-charge voltage (VBLP) has reached the desired level, thereby preventing malfunction of the sense amplifiers. The circuit includes: a VBB sensor for producing VBB set-up signal S1 when a back bias voltage VBB in the semiconductor memory device has reached a desired level; a power-up generator for producing a power-up signal S2 when power in the semiconductor memory device is set-up; a VBLP generator for generating a bit line pre-charge voltage VBLP; a VBLP controller for holding the VBLP voltage to a ground voltage level according to the S1 and S2 signals; a VBLP sensor for generating VBLP set-up signal S3 when the VBLP voltage has reached a desired level; a /RAS pass signal generator for producing a /RAS pass signal S4 according to the S3 and S2 signals; a NOR circuit for controlling the transmission of the /RAS signals according to the S 4 signal.
Abstract:
Apparatuses, methods and storage medium associated with 3D face model reconstruction are disclosed herein. In embodiments, an apparatus may include a facial landmark detector, a model fitter and a model tracker. The facial landmark detector may be configured to detect a plurality of landmarks of a face and their locations within each of a plurality of image frames. The model fitter may be configured to generate a 3D model of the face from a 3D model of a neutral face, in view of detected landmarks of the face and their locations within a first one of the plurality of image frames. The model tracker may be configured to maintain the 3D model to track the face in subsequent image frames, successively updating the 3D model in view of detected landmarks of the face and their locations within each of successive ones of the plurality of image frames. In embodiments, the facial landmark detector may include a face detector, an initial facial landmark detector, and one or more facial landmark detection linear regressors. Other embodiments may be described and/or claimed.
Abstract:
System, apparatus, method, and computer readable media for on-the-fly captured image data enhancement. An image or video stream is enhanced with a filter in concurrence with generation of the stream by a camera module. In one exemplary embodiment, HD image frames are filtered at a rate of 30 fps, or more, to enhance human skin tones with an edge-preserving smoothing filter. In embodiments, the smoothing filter is applied to an image representation of reduced resolution, reducing computational overhead of the filter. The filtered image is then upsampled and blended with a map that identifies edges to maintain an edge quality comparable to a smoothing filter applied at full resolution. A device platform including a camera module and comporting with the exemplary architecture may provide enhanced video camera functionality even at low image processing bandwidth.
Abstract:
According to a method for providing a notification on a face recognition environment of the present disclosure, the method includes obtaining an input image that is input in a preview state, comparing feature information for a face included in the input image with feature information for a plurality of reference images of people stored in a predetermined database to determine, in real-time, whether the input image satisfies a predetermined effective condition for photographing. The predetermined effective condition for photographing is information regarding a condition necessary for recognizing the face included in the input image at a higher accuracy level than a predetermined accuracy level. The method further includes providing a user with a predetermined feedback for photographing guidance that corresponds to whether the predetermined effective condition for photographing is satisfied. According to the method, a condition of a face image detected for face recognition is checked, and if there is an unsuitable element in recognizing the face, it is notified to a user such that an obstruction environment hindering the face recognition by the user is removed, for enhancing a success rate of the face recognition.
Abstract:
A liquid crystal display including a first substrate; a second substrate facing the first substrate; a thin film transistor disposed on the first substrate; an organic layer disposed on the thin film transistor; a pixel electrode disposed on the organic layer; a lower alignment layer disposed on the pixel electrode; a common electrode disposed on the second substrate; and an upper alignment layer disposed on the common electrode, wherein a first free radical included in the organic layer and a second free radical included in at least one of the lower alignment layer and the upper alignment layer are radical bonded.
Abstract:
Handheld wireless communications devices include a data input device, which is configured to receive first input data provided by a user, a main processor and a security processor. The security processor includes an input interface and input processing block configured to extract second data from a first portion of the first input data using, for example, a data mapping operation. The security processor also includes an encryption circuit, which is configured generate secure data from the extracted second data by encrypting the extracted second data using an encryption key, and a data/control interface, which is configured to transfer the secure data to the main processor.