Abstract:
A display may have upper and lower display layers. A layer of liquid crystal material may be interposed between the upper and lower display layers. The display layers may have substrates. A thin-film transistor layer may have a layer of thin-film transistor structures on a substrate such as a clear glass layer. A planarization layer may be formed on the thin-film transistor structures. A transparent conductive layer may be formed on the planarization layer. The display may have a dielectric layer on the transparent conductive layer. Pixels may be formed in the display layers. The pixels may include pixel electrodes having fingers. The fingers may be formed on the dielectric layer. Trenches in the dielectric layer may be formed between the fingers. The trenches may extend to the transparent conductive layer or may be formed only partway into the dielectric layer.
Abstract:
A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.
Abstract:
A display may have a thin-film transistor (TFT) layer and color filter layer. Light blocking structures in an inactive area of the display may prevent stray backlight from leaking out of the display. The thin-film transistor layer may have a first substrate, a first black masking layer, a planarization layer, and a layer of TFT circuitry on the planarization layer. The color filter layer may have a second substrate and a second black masking layer on the second substrate. Light-cured sealant may be formed between the TFT layer and the color filter layer. Gaps may be formed in the second black masking layer to allow light to cure the sealant. At least a portion of the TFT circuitry may serve to block stray backlight penetrating through the gaps in the second black masking layer during normal operation of the display.
Abstract:
A display may have an array of pixels. The array of pixels may have a shape such as a circular shape or other shape with a curved edge. Display driver circuitry may supply data signals to the pixels using folded vertical data lines and bisected horizontal gate lines. Each folded vertical lines may have a first segment in a left half of the array and a second segment in a right half of the display. Curved coupling segments in an inactive area of the display may be used in joining the first and second segments. Display driver circuits may be provided in top and bottom portions of the inactive area to supply data to respective top and bottom portions of the array. Gate driver output buffers may have different strengths in different rows of the array.
Abstract:
A display may have an array of pixels. The array of pixels may have a shape such as a circular shape or other shape with a curved edge. Display driver circuitry may supply data signals to the pixels using folded vertical data lines and bisected horizontal gate lines. Each folded vertical lines may have a first segment in a left half of the array and a second segment in a right half of the display. Curved coupling segments in an inactive area of the display may be used in joining the first and second segments. Display driver circuits may be provided in top and bottom portions of the inactive area to supply data to respective top and bottom portions of the array. Gate driver output buffers may have different strengths in different rows of the array.
Abstract:
A display may have upper and lower display layers. A layer of liquid crystal material may be interposed between the upper and lower display layers. The display layers may have substrates. A thin-film transistor layer may have a layer of thin-film transistor structures on a substrate such as a clear glass layer. A planarization layer may be formed on the thin-film transistor structures. A transparent conductive layer may be formed on the planarization layer The display may have a dielectric layer on the transparent conductive layer. Pixels may be formed in the display layers. The pixels may include pixel electrodes having fingers. The fingers may be formed on the dielectric layer. Trenches in the dielectric layer may be formed between the fingers. The trenches may extend to the transparent conductive layer or may be formed only partway into the dielectric layer.
Abstract:
A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be attached to a flexible printed circuit that is attached to the flexible substrate in the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be locally thinned in the bend region. A neutral stress plane adjustment layer may cover the metal traces in the bend region. The neutral stress plane adjustment layer may include polymer layers such as an encapsulation layer, a pixel definition layer, a planarization layer, and a layer that covers a pixel definition layer and planarization layer.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode and thin-film transistor circuitry that controls current flow through the organic light-emitting diode. The thin-film transistor circuitry may include silicon thin-film transistors and semiconducting-oxide thin-film transistors. Double gate transistor structures may be formed in the transistors of the thin-film transistor circuitry. A double gate transistor may have a semiconductor layer sandwiched between first and second dielectric layers. The first dielectric layer may be interposed between an upper gate and the semiconductor layer and the second dielectric layer may be interposed between a lower gate and the semiconductor layer. Capacitor structures may be formed from the layers of metal used in forming the upper and lower gates and other conductive structures.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have multiple subpixels of different colors. To avoid undesired color shifts when operating the display, the display may be configured so that subpixels of different colors are not coupled to each other through parasitic capacitances. The subpixels may include red, green, and blue subpixels or subpixels of other colors. Each subpixel may include an organic light-emitting diode having an anode and a cathode. The anode of each organic light-emitting diode may be coupled to a respective storage capacitor. Capacitive coupling between subpixels can be minimized by configuring the subpixel structures of each pixel so that the storage capacitors of the subpixels do not overlap the anodes of other subpixels in the pixel. Anode and capacitor overlap with subpixel data lines may also be reduced or eliminated.
Abstract:
A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.