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公开(公告)号：US11315654B2
公开(公告)日：2022-04-26
申请号：US16151220
申请日：2018-10-03
Applicant: Arm Limited
Abstract: Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.
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公开(公告)号：US20220122655A1
公开(公告)日：2022-04-21
申请号：US17071449
申请日：2020-10-15
Applicant: Arm Limited
Inventor： Rahul Mathur , Mudit Bhargava , Joel Thornton Irby , Andy Wangkun Chen
IPC: G11C11/418 , G11C11/419
Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.
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公开(公告)号：US11271567B1
公开(公告)日：2022-03-08
申请号：US17013199
申请日：2020-09-04
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Sriram Thyagarajan , Yew Keong Chong , Sony , Ettore Amirante , Ayush Kulshrestha
IPC: H03K19/17736 , H03K19/1776
Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.
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公开(公告)号：US20210333320A1
公开(公告)日：2021-10-28
申请号：US16857144
申请日：2020-04-23
Applicant: Arm Limited
Inventor： Sriram Thyagarajan , Pratik Ghanshambhai Satasia , Yew Keong Chong , Andy Wangkun Chen , Mouli Rajaram Chollangi
IPC: G01R31/28 , G06F30/3312
Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.
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公开(公告)号：US11068639B2
公开(公告)日：2021-07-20
申请号：US16165675
申请日：2018-10-19
Applicant: Arm Limited
Inventor： Marlin Wayne Frederick, Jr. , Ettore Amirante , Ronald Paxton Preston , Andy Wangkun Chen , Sriram Thyagarajan , Yew Keong Chong
IPC: G06F30/39 , G06F30/394 , G11C11/419 , G11C7/12
Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.
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Patent Agency Ranking
公开(公告)号：US20210193195A1
公开(公告)日：2021-06-24
申请号：US16725779
申请日：2019-12-23
Applicant: Arm Limited
Inventor： Sriram Thyagarajan , Andy Wangkun Chen , Yew Keong Chong , Munish Kumar
IPC: G11C7/10
Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.
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公开(公告)号：US20210157603A1
公开(公告)日：2021-05-27
申请号：US16698862
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Shardendu Shekhar , Andy Wangkun Chen , Anil Kumar Baratam , James Dennis Dodrill , Yew Keong Chong
Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.
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公开(公告)号：US11005461B2
公开(公告)日：2021-05-11
申请号：US16004009
申请日：2018-06-08
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Sai Sriharsha Manapragada , Yicong Li , Yew Keong Chong , Bikas Maiti , Sanjay Mangal , Hsin-Yu Chen
Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.
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公开(公告)号：US10984863B2
公开(公告)日：2021-04-20
申请号：US15959048
申请日：2018-04-20
Applicant: Arm Limited
Inventor： Mohammed Saif Kunjatur Sheikh , Vikash , Andy Wangkun Chen
Abstract: Various implementations described herein are directed to an integrated circuit having an array of bitcells. The integrated circuit may include latch circuitry having a latch for each row of bitcells that latches valid match data into the latch for each row of bitcells. The integrated circuit may include priority encoding circuitry that receives the valid match data from the latch for each row of bitcells. The integrated circuit may include first logic circuitry coupled between the array of bitcells and the priority encoding circuitry to assist with providing the valid match data to the latch circuitry.
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公开(公告)号：US10978141B1
公开(公告)日：2021-04-13
申请号：US16698851
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Yew Keong Chong , Sriram Thyagarajan , Andy Wangkun Chen , Vivek Asthana , Munish Kumar
IPC: G11C11/418 , G11C11/417 , G11C11/419
Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.
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