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15 条记录 (耗时 0.017 秒)

    Error detection and correction circuitry
    2.
    发明授权
    Error detection and correction circuitry 有权

    公开(公告)号：US10984863B2

    公开(公告)日：2021-04-20

    申请号：US15959048

    申请日：2018-04-20

    申请人： Arm Limited

    发明人： Mohammed Saif Kunjatur Sheikh ,  Vikash ,  Andy Wangkun Chen

    IPC分类号： G11C15/04 ,  G11C29/42 ,  G06F11/10

    摘要： Various implementations described herein are directed to an integrated circuit having an array of bitcells. The integrated circuit may include latch circuitry having a latch for each row of bitcells that latches valid match data into the latch for each row of bitcells. The integrated circuit may include priority encoding circuitry that receives the valid match data from the latch for each row of bitcells. The integrated circuit may include first logic circuitry coupled between the array of bitcells and the priority encoding circuitry to assist with providing the valid match data to the latch circuitry.

    Non-discharging read-only memory cells
    6.
    发明授权
    Non-discharging read-only memory cells 有权

    公开(公告)号：US09697908B1

    公开(公告)日：2017-07-04

    申请号：US15179686

    申请日：2016-06-10

    申请人： ARM Limited

    发明人： Kapil Rathi ,  Abhishek Kumar Shrivastava ,  Vikash

    IPC分类号： G11C17/00 ,  G11C17/08 ,  G11C13/00 ,  G11C17/12 ,  G11C17/10

    CPC分类号： G11C17/08 ,  G11C13/0007 ,  G11C17/10 ,  G11C17/12 ,  G11C17/123

    摘要： Various implementations described herein may refer to and may be directed to non-discharging read-only memory cells. For instance, in one implementation, an integrated circuit may include a read-only memory (ROM) array including a plurality of ROM cells arranged into a column, where the column is disposed proximate to a bit line and to a reference voltage line. The plurality of ROM cells arranged into the column may include a plurality of non-discharging ROM cells positioned adjacently to one another, where each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell. In addition, the plurality of non-discharging ROM cells may be coupled to the bit line using two or fewer connections.

    Double Pumped Memory Techniques
    7.
    发明申请
    Double Pumped Memory Techniques 有权
    双抽液记忆技术

    公开(公告)号：US20160064054A1

    公开(公告)日：2016-03-03

    申请号：US14836657

    申请日：2015-08-26

    申请人： ARM Limited

    发明人： Andy Wangkun Chen ,  Hsin-Yu Chen ,  Sabarish Ittamveetil ,  Yew Keong Chong ,  Indranil Basu ,  Vikash

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/06

    CPC分类号： G11C8/18 ,  G06F13/28 ,  G11C5/025 ,  G11C7/062 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/12

    摘要： A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.

    摘要翻译： 提供了一种操作存储器件的存储器件和方法。 存储器件包括被配置为接收存储器件的时钟信号的全局控制电路，并且存储器件配置为响应于时钟信号的单个边沿执行双存储器访问。 响应于时钟信号的单个边沿而产生用于双存储器存取的第一次访问的第一内部时钟脉冲和用于双存储器访问的第二访问的第二内部时钟脉冲。 全局控制电路根据由第一访问指示的第一组与由第二访问指示的第二组之间的比较产生比较信号，并且第二组的本地组控制电路被配置为产生第二内部时钟脉冲 依赖于比较信号。

    Voltage aware circuitry
    8.
    发明授权
    Voltage aware circuitry 有权

    公开(公告)号：US09767870B1

    公开(公告)日：2017-09-19

    申请号：US15238551

    申请日：2016-08-16

    申请人： ARM Limited

    发明人： Rajiv Kumar Roy ,  Kanika Malik ,  Manoj Puthan Purayil ,  Vikash

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C8/10

    CPC分类号： G11C5/14 ,  G11C7/065 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/417 ,  G11C11/418

    摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry having an array of memory cells and a row decoder that accesses each of the memory cells via a selected wordline and a wordline signal. The core circuitry may operate at a first supply voltage. The integrated circuit may include periphery circuitry having a column decoder that accesses each of the memory cells via a selected bitline. The periphery circuitry may operate at a second supply voltage that is different than the first supply voltage. The periphery circuitry may include voltage differential sensing circuitry that may compare the first supply voltage to the second supply voltage, sense a voltage differential between the first and second supply voltages, and delay the wordline signal when the voltage differential is greater than a threshold voltage.

    Read-write contention circuitry
    10.
    发明授权
    Read-write contention circuitry 有权
    读写争用电路

    公开(公告)号：US09478278B1

    公开(公告)日：2016-10-25

    申请号：US14675687

    申请日：2015-03-31

    申请人： ARM Limited

    发明人： Rejeesh Ammanath Vijayan ,  Vikash ,  Pradeep Raj ,  Neelima Gudipati ,  Manish Trivedi ,  Sujit Rout

    IPC分类号： G11C11/00 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C8/16

    摘要： Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

    摘要翻译： 本文描述的各种实现涉及用于读写争用的集成电路。 集成电路可以包括具有被配置为接收对应于每个端口的数据信号的多个端口的存储器电路。 集成电路可以包括争用覆盖电路，其基于检测端口之间的读写争用，为每个端口提供争用覆盖信号。 集成电路可以包括具有用于每个端口的多个通行口的写入电路，包括用于每个端口的写通行证和争用通行证。 写入通道可以用来自相应端口的数据信号输入。 可以基于相对的争用覆盖信号，从相对端口输入具有数据信号的争用通行证。