公开(公告)号：US08232599B2

公开(公告)日：2012-07-31

申请号：US12683456

申请日：2010-01-07

Applicant: Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC: H01L27/12 ,  H01L21/86

CPC classification number: H01L27/1207 ,  H01L21/84

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract translation: 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US20120187492A1

公开(公告)日：2012-07-26

申请号：US13425681

申请日：2012-03-21

Applicant: Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC: H01L27/088

CPC classification number: H01L27/1207 ,  H01L21/84

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract translation: 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US08132267B2

公开(公告)日：2012-03-06

申请号：US12286352

申请日：2008-09-30

Applicant: Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J Parker

Inventor： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J Parker

IPC: G06F11/00

CPC classification number: G06F21/88 ,  G06F9/4401 ,  G06F9/44542 ,  G06F21/575 ,  G06F21/73 ,  G06F2221/2141

Abstract: In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.

Abstract translation: 在一些实施例中，基于处理器的系统可以包括处理器，处理器具有处理器标识，耦合到处理器的一个或多个电子部件，具有部件识别的电子部件中的至少一个以及耦合到 处理器和电子元件。 硬件安全组件可以包括安全的非易失性存储器和控制器。 控制器可以被配置为从处理器接收处理器标识，从一个或多个电子部件接收至少一个组件标识，并且确定基于处理器的系统的启动是否是基于处理器的系统的供应引导 。 如果确定引导是供应启动，则控制器可以被配置为将安全代码存储在安全非易失性存储器中，其中安全代码基于处理器标识和至少一个组件标识。 公开和要求保护其他实施例。

公开(公告)号：US20110145598A1

公开(公告)日：2011-06-16

申请号：US12639616

申请日：2009-12-16

Applicant: Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

Inventor： Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

IPC: G06F9/30 ,  G06F21/22 ,  G06F9/02 ,  G06F15/76 ,  G06F1/32

CPC classification number: G06F21/554 ,  G06F21/44 ,  G06F21/57 ,  G06F21/64

Abstract: In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括微代码存储器，其包括处理器指令，用于创建和执行在系统软件不可见的隐藏环境中执行的隐藏资源管理器（HRM）。 处理器还可以包括扩展寄存器，用于存储包括隐藏环境的至少一个内核代码模块的测量值和至少一个内核代码模块的验证状态的安全信息。 描述和要求保护其他实施例。

公开(公告)号：US20110089499A1

公开(公告)日：2011-04-21

申请号：US12581924

申请日：2009-10-20

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

公开(公告)号：US20100331368A1

公开(公告)日：2010-12-30

申请号：US12680844

申请日：2008-10-17

Applicant: Richard R. Tidwell ,  David W. Boykin ,  Chad E. Stephens ,  Mohamed A. Ismail ,  Arvind Kumar ,  W. David Wilson ,  Reto Brun ,  Karl Werbovetz

Inventor： Richard R. Tidwell ,  David W. Boykin ,  Chad E. Stephens ,  Mohamed A. Ismail ,  Arvind Kumar ,  W. David Wilson ,  Reto Brun ,  Karl Werbovetz

IPC: A61K31/444 ,  C07D345/00 ,  A61K31/33 ,  A61K31/4427 ,  C07D421/04 ,  C07D421/14 ,  C07D409/14 ,  A61P31/00 ,  A61P33/02

CPC classification number: C07D345/00 ,  C07D409/14 ,  C07D421/04 ,  C07D421/14

Abstract: Novel dicationic 2,5-diaryl selenophene compounds are described. Also described are novel aza analogues of dicationic 2,5-diaryl thiophenes. The presently disclosed dicationic compounds exhibit in vitro activity versus Trypanosoma brucei rhodesiense, Plasmodium falciparum, and/or Leishmania donovani comparable to that of pentamidine and furamidine. Some of the novel dicationic compounds display good activity in vivo in a murine model of a Trypanosoma brucei rhodesiense infection.

Abstract translation: 描述了新型的阳离子2,5-二芳基硒吩化合物。 还描述了双阳离子2,5-二芳基噻吩的新型氮杂类似物。 目前公开的阳离子化合物显示体外活性与罗氏黑斑病，恶性疟原虫和/或与烟脒和呋脒类似的杜氏利什曼原虫的体外活性。 一些新型阳离子化合物在罗氏黑斑病感染的鼠模型中在体内表现出良好的活性。

公开(公告)号：US20090175781A1

公开(公告)日：2009-07-09

申请号：US12240762

申请日：2008-09-29

Applicant: Arvind Kumar ,  Indrajit Mukhopadhyay ,  Pushpito Kumar Ghosh ,  Vadakke Puthoor Mohandas ,  Jignesh Jasvantrai Shukla ,  Rahul Jasvantrai Sanghavi

Inventor： Arvind Kumar ,  Indrajit Mukhopadhyay ,  Pushpito Kumar Ghosh ,  Vadakke Puthoor Mohandas ,  Jignesh Jasvantrai Shukla ,  Rahul Jasvantrai Sanghavi

IPC: C01D3/06

CPC classification number: C01D3/16 ,  C01D3/06

Abstract: The process of the invention is an improvement over the existing process of producing salt of high purity from alum-treated brine disclosed recently in the prior art. More particularly, the invention rectifies the ratio of Ca2+ to Mg2+ from a value

Abstract translation: 本发明的方法是相对于现有技术中最近公开的由明矾处理的卤水生产高纯度盐的现有方法的改进。 更具体地说，本发明将Ca2 +与Mg2 +的比值从值<1改为由氯碱和苏打灰工业所要求的2-3的范围内的值。 改进的方法包括用HCl水溶液调节澄清盐水的pH，以便在pH6.5下进行盐结晶，而不是在7的天然pH下进行盐结晶。pH调节降低了盐中的Mg 2+杂质，同时略微提高了Ca2 +杂质 在盐中，从而达到所需的比例。

公开(公告)号：US20090121258A1

公开(公告)日：2009-05-14

申请号：US11939017

申请日：2007-11-13

Applicant: Arvind Kumar

Inventor： Arvind Kumar

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

Abstract translation: 提供了包括硅含量体的场效应晶体管。 在形成栅极电介质，栅极电极和第一栅极间隔物之后，形成漏极侧沟槽并填充宽带隙半导体材料。 可选地，可以形成源极沟槽并填充硅锗合金以增强场效应晶体管的导通电流。 进行光晕注入和源极和漏极离子注入以形成各种掺杂区域。 由于宽带隙半导体材料作为比硅的带隙宽的带隙，由于在漏极中使用宽带隙半导体材料，因此冲击电离降低，因此，场效应晶体管的击穿电压比较 涉及在漏极区域中使用硅的晶体管。

公开(公告)号：US20090108373A1

公开(公告)日：2009-04-30

申请号：US11927964

申请日：2007-10-30

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Jeffrey Sleight

IPC: H01L27/11 ,  H01L21/8244

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US07437566B2

公开(公告)日：2008-10-14

申请号：US10837131

申请日：2004-05-01

Applicant: Kevin R. Moore ,  Peyman Oreizy ,  Sean O. Blagsvedt ,  Arvind Kumar

Inventor： Kevin R. Moore ,  Peyman Oreizy ,  Sean O. Blagsvedt ,  Arvind Kumar

IPC: G06F9/00

CPC classification number: H04L63/126 ,  H04L9/3236 ,  H04L9/3297 ,  H04L2209/60 ,  H04L2209/80

Abstract: A system and method is provided for confirmation of the identity of a contact on the network. A notification that a nearby user is present on a network is signed with a private key associated with the nearby user. The private key is also associated with a public key. A local user that has the nearby user's public key can verify the signature on the notification and confirm that the nearby user is the source of the notification. The verification of identity of the nearby user allows rich content previously stored for the nearby user to be displayed along with the nearby user's presence information.

Abstract translation: 提供了用于确认网络上的联系人身份的系统和方法。 附近用户在网络上的通知用与附近用户相关联的私钥进行签名。 私钥也与公钥相关联。 具有附近用户公钥的本地用户可以验证通知上的签名，并确认附近用户是通知的来源。 对附近用户的身份的验证允许与附近用户的存在信息一起显示先前为附近用户存储的丰富内容。