公开(公告)号：US20090080245A1

公开(公告)日：2009-03-26

申请号：US11861135

申请日：2007-09-25

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C5/02 ,  G11C16/04 ,  H01L21/8247

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

摘要翻译： 公共活动层上的多个非易失性存储元件偏离邻近的非易失性存储元件。 非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。 还描述了制造偏移非易失性存储元件的制造方法。

公开(公告)号：US07508720B2

公开(公告)日：2009-03-24

申请号：US11316475

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

摘要翻译： 根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。 在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。 例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。 如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。 通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。 例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。 这样的字符串可能是有缺陷的，并被映射出存储器件。

公开(公告)号：US20090010065A1

公开(公告)日：2009-01-08

申请号：US12211348

申请日：2008-09-16

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/10

CPC分类号： G11C16/3418

摘要： A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种减少程序干扰的非易失性存储系统。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US07463531B2

公开(公告)日：2008-12-09

申请号：US11618606

申请日：2006-12-29

申请人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

公开(公告)号：US07460404B1

公开(公告)日：2008-12-02

申请号：US11745082

申请日：2007-05-07

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

IPC分类号： G11C16/00

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

摘要翻译： 在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。 使用包括隔离字线的自增强模式。 禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。 此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。 以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。 在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

公开(公告)号：US20080291736A1

公开(公告)日：2008-11-27

申请号：US11753963

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/12

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。

公开(公告)号：US07450435B2

公开(公告)日：2008-11-11

申请号：US11316162

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

摘要翻译： 根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。 在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。 例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。 如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。 通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。 例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。 这样的字符串可能是有缺陷的，并被映射出存储器件。

公开(公告)号：US07440319B2

公开(公告)日：2008-10-21

申请号：US11563590

申请日：2006-11-27

申请人： Yan Li ,  Teruhiko Kamei ,  Jeffrey W. Lutze

发明人： Yan Li ,  Teruhiko Kamei ,  Jeffrey W. Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/3445 ,  G06F11/1072 ,  G11C16/344 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/72 ,  G11C29/808

摘要： A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed.

摘要翻译： 一组非易失性存储元件经受编程处理以便存储一组数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。 关于是继续编程还是编程成功的决定是基于非易失性存储元件的重叠组是否具有小于非正确编程的非易失性存储元件的阈值数量来进行。

公开(公告)号：US20080124865A1

公开(公告)日：2008-05-29

申请号：US12024787

申请日：2008-02-01

申请人： Jeffrey W. Lutze ,  Nima Mokhlesi

发明人： Jeffrey W. Lutze ,  Nima Mokhlesi

IPC分类号： H01L21/336

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

摘要： A memory system is disclosed that includes a set of non-volatile storage elements. Each of the non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 每个非易失性存储元件包括在衬底中的沟道的相对侧处的源极/漏极区域以及在沟道上方的浮动栅极堆叠。 存储器系统还包括位于相邻浮动栅极堆叠之间并电连接到源极/漏极区域的一组屏蔽板，用于减少相邻浮动栅极之间的耦合。 屏蔽板选择性地生长在存储器的有效区域上，而不会在非活动区域上生长。 在一个实施例中，屏蔽板是位于源/漏区上方的外延生长的硅。

公开(公告)号：US07286406B2

公开(公告)日：2007-10-23

申请号：US11250735

申请日：2005-10-14

申请人： Jeffrey W. Lutze ,  Yan Li ,  Siu L. Chan

发明人： Jeffrey W. Lutze ,  Yan Li ,  Siu L. Chan

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

摘要翻译： 解决位线对位线耦合在非易失性存储器中的影响。 在编程的存储元件的位线上施加禁止电压，以在编程电压的一部分期间禁止编程。 随后在编程电压期间去除抑制电压以允许编程发生。 由于位线的接近，位线电压的变化被耦合到相邻的未选位线，将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。 为了防止这种情况，在位线电压变化期间临时调整选择栅极电压，以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。