公开(公告)号：US20100068841A1

公开(公告)日：2010-03-18

申请号：US12433743

申请日：2009-04-30

申请人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You ,  Jae-Byoung Chae ,  Tae-Ill Kim

发明人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You ,  Jae-Byoung Chae ,  Tae-Ill Kim

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上形成多晶硅半导体层; 在所述半导体层上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 通过掺杂半导体层中的导电杂质形成源区和漏区; 形成覆盖所述栅电极的层间绝缘层; 形成分别连接到源区和漏区的源电极和漏电极; 形成覆盖源极和漏极的钝化层; 形成连接到所述漏电极的像素电极; 以及在形成从半导体层，栅电极，源极和漏极以及像素电极中选择的一个时形成第一对准键，其中从半导体层，栅电极，源电极和漏电极中选择一个， 并且至少通过使用光致抗蚀剂图案作为蚀刻掩模的光刻工艺形成像素电极，并且在与光致抗蚀剂图案相同的层处形成完全覆盖第一对准键的第二对准键。

公开(公告)号：US07675065B2

公开(公告)日：2010-03-09

申请号：US11671727

申请日：2007-02-06

申请人： Chun-Gi You ,  Bong-Ju Kim

发明人： Chun-Gi You ,  Bong-Ju Kim

IPC分类号： H01L31/00

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor (TFT) array panel includes a substrate, a first signal line formed on the substrate, a gate insulating layer formed on the first signal line and having a first contact hole exposing a portion of the first signal line, a first semiconductor formed on the gate insulating layer, a second signal line formed on the first semiconductor and the gate insulating layer and a drain electrode formed on the first semiconductor and separated from the second signal line. The TFT array panel further includes a conductor formed on the gate insulating layer and connected to the first signal line through the first contact hole, a passivation layer formed on the second signal line, the drain electrode, and the conductor, and having a second contact hole exposing the drain electrode and a pixel electrode formed on the passivation layer and connected to the drain electrode through the second contact hole.

摘要翻译： 薄膜晶体管（TFT）阵列面板包括基板，形成在基板上的第一信号线，形成在第一信号线上并具有暴露第一信号线的一部分的第一接触孔的栅绝缘层，第一半导体 形成在所述栅极绝缘层上，形成在所述第一半导体和所述栅极绝缘层上的第二信号线和形成在所述第一半导体上并与所述第二信号线分离的漏电极。 TFT阵列板还包括形成在栅极绝缘层上并通过第一接触孔连接到第一信号线的导体，形成在第二信号线，漏极和导体上的钝化层，并具有第二接触 漏极电极和形成在钝化层上并通过第二接触孔连接到漏电极的像素电极。

公开(公告)号：US07608493B2

公开(公告)日：2009-10-27

申请号：US11944010

申请日：2007-11-21

申请人： Seong-Kweon Heo ,  Chun-Gi You

发明人： Seong-Kweon Heo ,  Chun-Gi You

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： A thin-film transistor substrate includes a gate line, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data line, a protection layer, and a pixel electrode. The gate wiring including a gate electrode, a lower storage electrode, and a gate metal pad is disposed on a substrate. The capacitor dielectric layer is disposed on the lower storage electrode and the gate insulation layer is disposed on the substrate. The active pattern includes an active layer and a dummy active layer disposed on the gate insulation layer in a gate electrode region and a gate metal pad region, respectively. A portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through a first contact hole in the gate insulation layer.

摘要翻译： 薄膜晶体管基板包括栅极线，电容器电介质层，栅极绝缘层，有源图案，数据线，保护层和像素电极。 包括栅电极，下存储电极和栅极金属焊盘的栅极布线设置在基板上。 电容器电介质层设置在下部存储电极上，栅极绝缘层设置在基板上。 有源图案包括分别设置在栅极电极区域和栅极金属焊盘区域中的栅极绝缘层上的有源层和伪有源层。 上部存储电极的一部分设置在通过栅极绝缘层中的第一接触孔露出的电容器电介质层上。

公开(公告)号：US07560316B2

公开(公告)日：2009-07-14

申请号：US11871027

申请日：2007-10-11

申请人： Seong-Kweon Heo ,  Chun-Gi You ,  Min-Hyuk Choi

发明人： Seong-Kweon Heo ,  Chun-Gi You ,  Min-Hyuk Choi

IPC分类号： H01L21/84 ,  H01L33/00

CPC分类号： G02F1/13458 ,  G02F1/133555 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes interconnection members interposed between the underlying gate pads made of an Al-containing metal and the overlying contact assistants made of a transparent conductor such as ITO thereon to prevent corrosion of Al due to ITO, or gate-layer signal transmission lines. Gate-layer signal transmission lines are directly connected to the data-layer signal transmission line to prevent corrosion of Al due to ITO in the thin film transistor array panel according to an embodiment of the present invention. The color filters are formed on the thin film transistor array panel to prevent misalignment between the two display panels so as to increase the aperture ratio.

摘要翻译： 薄膜晶体管阵列面板包括插入在由含Al金属制成的下面的栅极焊盘之间的互连部件和由诸如ITO的透明导体制成的上覆触点辅助件，以防止由于ITO导致的Al的腐蚀或栅极层信号 传输线。 栅极层信号传输线直接连接到数据层信号传输线，以防止根据本发明实施例的薄膜晶体管阵列面板中由ITO引起的Al的腐蚀。 滤色器形成在薄膜晶体管阵列面板上，以防止两个显示面板之间的不对准，从而增加开口率。

公开(公告)号：US07486367B2

公开(公告)日：2009-02-03

申请号：US10986651

申请日：2004-11-12

申请人： Chun-Gi You

发明人： Chun-Gi You

IPC分类号： G02F1/1345 ,  G02F1/1333 ,  G09G3/30 ,  H01L27/14

CPC分类号： G02F1/136213 ,  G02F1/13458 ,  G02F1/136227 ,  H01L27/3276

摘要： A display panel including first to third conductive films is provided, which includes: a first signal line including a first portion that includes the first conductive film, an intermediate portion that includes at least two of the first to the third conductive films (“intermediate portion films”), and a contact portion that contacts an output terminal of a driving circuit and includes the intermediate portion films except for at least one of the intermediate portion films; a second signal line intersecting the first signal line and including the second conductive film; a switching element connected to the first and the second signal lines; and a pixel electrode connected to the switching element and including the third conductive film.

摘要翻译： 提供了包括第一至第三导电膜的显示面板，其包括：第一信号线，包括包括第一导电膜的第一部分，包括第一至第三导电膜中的至少两个的中间部分（“中间部分 薄膜“）和接触部分，其接触驱动电路的输出端子并且包括除中间部分薄膜中的至少一个以外的中间部分薄膜; 与第一信号线相交并且包括第二导电膜的第二信号线; 连接到第一和第二信号线的开关元件; 以及连接到开关元件并包括第三导电膜的像素电极。

公开(公告)号：US20090026463A1

公开(公告)日：2009-01-29

申请号：US12173476

申请日：2008-07-15

申请人： Jin-Hee Kang ,  Chun-Gi You ,  Seong-Kweon Heo

发明人： Jin-Hee Kang ,  Chun-Gi You ,  Seong-Kweon Heo

IPC分类号： H01L33/00 ,  H01L21/20

CPC分类号： H01L27/1248

摘要： An array substrate includes a thin-film transistor (TFT), a first insulation layer and a second insulation layer. The TFT is formed on the substrate. The TFT includes an active pattern, a gate metal pattern and a data metal pattern. The first insulation layer insulates the active pattern from the gate metal pattern. The second insulation layer is formed spaced apart by a predetermined width from at least one edge of the substrate. The second insulation layer insulates the gate metal pattern from the data metal pattern. Therefore, the second insulation layer is formed so that stress that is inflicted on a substrate may be decreased, thereby preventing deformation during a manufacturing process of the substrate.

摘要翻译： 阵列衬底包括薄膜晶体管（TFT），第一绝缘层和第二绝缘层。 在基板上形成TFT。 TFT包括有源图案，栅极金属图案和数据金属图案。 第一绝缘层将活性图案与栅极金属图案绝缘。 第二绝缘层与衬底的至少一个边缘间隔开预定的宽度。 第二绝缘层将栅极金属图案与数据金属图案绝缘。 因此，第二绝缘层形成为使得在基板上施加的应力可能降低，从而防止在基板的制造过程中的变形。

公开(公告)号：US07479416B2

公开(公告)日：2009-01-20

申请号：US11330312

申请日：2006-01-10

申请人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You

发明人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F1/136227 ,  H01L27/1214 ,  H01L27/3244 ,  H01L51/56

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent conductive layer on the first passivation layer; etching the transparent conductive layer using a photoresist as an etch mask to expose the portion of the first passivation layer and to form a pixel electrode connected the drain electrode; ashing the first passivation layer and the photoresist; and removing the photoresist.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在衬底上形成包括栅电极，漏电极，源电极和半导体的薄膜晶体管; 在漏极和源电极上形成第一钝化层; 在所述第一钝化层上形成透明导电层; 使用光致抗蚀剂蚀刻透明导电层作为蚀刻掩模以暴露第一钝化层的部分并形成连接漏电极的像素电极; 灰化第一钝化层和光致抗蚀剂; 并去除光致抗蚀剂。

公开(公告)号：US20080061446A1

公开(公告)日：2008-03-13

申请号：US11939975

申请日：2007-11-14

申请人： Chun-Gi You

发明人： Chun-Gi You

IPC分类号： H01L23/52

CPC分类号： H01L29/66765 ,  H01L21/76804 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited thereon after forming data lines and drain electrodes. The upper insulating layer is patterned to form an unevenness pattern on its surface and contact holes on the drain electrodes. The lower insulating layer is patterned together with the gate insulating layer using a photoresist pattern having apertures located in the contact holes to form other contact holes respectively exposing the drain electrodes, portions of the gate lines, and portions of the data lines. After forming transparent electrodes and contact assistants respectively connected to the drain electrodes and the gate and the data lines through the contact holes, reflecting electrodes having apertures are formed on the transparent electrodes.

摘要翻译： 在基板上形成多条栅极线。 在沉积栅极绝缘层之后，依次形成半导体层和掺杂的非晶硅层。 在形成数据线和漏电极之后，沉积由氮化硅制成的下绝缘层和由光敏有机材料制成的上绝缘层。 上绝缘层被图案化以在其表面上形成凹凸图案并且在漏电极上形成接触孔。 使用具有位于接触孔中的孔的光致抗蚀剂图案，将下绝缘层与栅绝缘层一起构图，以形成分别暴露漏电极，栅线部分和数据线的一部分的其他接触孔。 在形成透明电极和分别连接到漏电极和栅极和数据线的接触辅助件之间通过接触孔形成透明电极上形成有孔的反射电极。

公开(公告)号：US20080017855A1

公开(公告)日：2008-01-24

申请号：US11780952

申请日：2007-07-20

申请人： Bong-Ju Kim ,  Min-Hyuk Choi ,  Chun-Gi You ,  Young-II Kim

发明人： Bong-Ju Kim ,  Min-Hyuk Choi ,  Chun-Gi You ,  Young-II Kim

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L33/00

CPC分类号： G02F1/1309 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286

摘要： A display substrate includes a pixel, a signal transmission line, a first insulating layer and a test signal input part. The pixel is on an insulating substrate. The signal transmission line is on the insulating substrate to transmit an image signal. The first insulating layer is on the signal transmission line. The first insulating layer has a contact hole through which the signal transmission line is partially exposed. The test signal input part is on the first insulating layer, and includes an extended portion and a test signal pad. The extended portion is electrically connected to the signal transmission line through the contact hole, and is extended toward a side of the insulating substrate. The test signal pad is electrically connected to the extended portion. Therefore, the number of defects is decreased.

摘要翻译： 显示基板包括像素，信号传输线，第一绝缘层和测试信号输入部。 像素在绝缘基板上。 信号传输线在绝缘基板上，以传输图像信号。 第一绝缘层位于信号传输线上。 第一绝缘层具有接触孔，信号传输线通过该接触孔部分露出。 测试信号输入部分在第一绝缘层上，并且包括延伸部分和测试信号焊盘。 延伸部分通过接触孔电连接到信号传输线，并且朝向绝缘基板的一侧延伸。 测试信号垫电连接到延伸部分。 因此，缺陷的数量减少。

公开(公告)号：US20070296003A1

公开(公告)日：2007-12-27

申请号：US11760495

申请日：2007-06-08

申请人： Gyung-Soon Park ,  Chun-Gi You ,  Kyung-Kim Park ,  Hyun-Sik Yoon

发明人： Gyung-Soon Park ,  Chun-Gi You ,  Kyung-Kim Park ,  Hyun-Sik Yoon

IPC分类号： H01L29/76

CPC分类号： H01L29/4908 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/78621

摘要： A thin-film transistor (TFT) substrate includes a base substrate, a semiconductor layer, a gate insulating layer, a first gate electrode and a second gate electrode. The semiconductor layer is formed on the base substrate and includes source, drain, channel and low concentration doped regions. The channel region is formed between the source and drain regions. The low concentration doped region is formed between the source and channel regions and between the drain and channel regions. The gate insulating layer is formed on the semiconductor layer. The first gate electrode is formed on the gate insulating layer to be overlapped with the channel region. The second gate electrode is formed on the second gate electrode. The gate insulating layer includes first and second regions, and a thickness of the first region is thinner than that of the second region. Thus, electric characteristics of the TFT may be enhanced.

摘要翻译： 薄膜晶体管（TFT）基板包括基底基板，半导体层，栅极绝缘层，第一栅电极和第二栅电极。 半导体层形成在基底衬底上，包括源极，漏极，沟道和低浓度掺杂区域。 沟道区形成在源区和漏区之间。 在源极和沟道区之间以及漏极和沟道区之间形成低浓度掺杂区。 栅极绝缘层形成在半导体层上。 第一栅电极形成在栅极绝缘层上以与沟道区重叠。 第二栅电极形成在第二栅电极上。 栅极绝缘层包括第一和第二区域，并且第一区域的厚度比第二区域的厚度薄。 因此，可以提高TFT的电特性。