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    Defending against DoS attacks over RDMA connections
    122.
    发明授权
    Defending against DoS attacks over RDMA connections 有权

    公开(公告)号：US10250635B2

    公开(公告)日：2019-04-02

    申请号：US15652285

    申请日：2017-07-18

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Alex Shpiner ,  Liran Liss ,  Matty Kadosh

    IPC: H04L29/06

    Abstract: A processor is configured to receive, from a client, a first message indicating a request to establish a connection between the client and a server, to ascertain that the first message does not include any cookie satisfying one or more criteria, to send, to the client, a second message that includes a first cookie, without allocating an endpoint on the server for the connection, in response to ascertaining that the first message does not include any cookie satisfying the criteria, to receive subsequently, from the client, a third message, to ascertain that the third message includes a second cookie, and that the second cookie satisfies the criteria, to allocate the endpoint for the connection in response to ascertaining that the second cookie satisfies the criteria, and to send, to the client, a fourth message indicating that the server is ready to receive data communication at the allocated endpoint.

    Host bus access by add-on devices via a network interface controller
    123.
    发明授权
    Host bus access by add-on devices via a network interface controller 有权

    公开(公告)号：US10152441B2

    公开(公告)日：2018-12-11

    申请号：US15154945

    申请日：2016-05-14

    Applicant: Mellanox Technologies Ltd.

    Inventor： Liran Liss ,  Shachar Raindel ,  Shlomo Raikin ,  Adi Menachem ,  Yuval Itkin

    IPC: G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  G06F13/28 ,  H04L12/861 ,  G06F13/40 ,  H04L12/935

    Abstract: Peripheral apparatus for use with a host computer includes an add-on device, which includes a first network port coupled to one end of a packet communication link and add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data. A network interface controller (NIC) includes a host bus interface, configured for connection to the host bus of the host computer and a second network port, coupled to the other end of the packet communication link. Packet processing logic in the NIC is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the resources of the host computer.

    Remote host management over a network
    124.
    发明授权
    Remote host management over a network 有权

    公开(公告)号：US10146721B2

    公开(公告)日：2018-12-04

    申请号：US15051750

    申请日：2016-02-24

    Applicant: Mellanox Technologies Ltd.

    Inventor： Yuval Itkin ,  Liran Liss ,  Amir Ancel ,  Ran Sofer

    IPC: G06F15/173 ,  G06F13/42 ,  G06F13/36 ,  G06F13/40

    Abstract: A method for management of a host computer that includes a management controller configured to carry out, independently of the host CPU, host management instructions contained in management packets compliant with a first data link protocol. The method includes receiving the management packets from a first network operating in accordance with the first data link protocol. The management packets are encapsulated in data packets compliant with a second data link protocol, different from the first data link protocol. The data packets are transmitted to a second network, operating in accordance with the second data link protocol. The transmitted data packets are received from the second network in a network interface controller (NIC), which is installed in the host computer and connected to the second network. The NIC decapsulates the management packets from the received data packets and passes the decapsulated management packets via a sideband connection to the management controller.

    Network-based computational accelerator
    125.
    发明授权
    Network-based computational accelerator 有权

    公开(公告)号：US10135739B2

    公开(公告)日：2018-11-20

    申请号：US15145983

    申请日：2016-05-04

    Applicant: Mellanox Technologies Ltd.

    Inventor： Shachar Raindel ,  Shlomo Raikin ,  Liran Liss

    IPC: H04L29/06 ,  H04L12/801 ,  H04L29/08 ,  G06F21/60 ,  H04L12/851

    Abstract: A data processing device includes a first packet communication interface for communication with at least one host processor via a network interface controller (NIC) and a second packet communication interface for communication with a packet data network. A memory holds a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second interfaces packet communication interfaces. Acceleration logic, coupled between the first and second packet communication interfaces, performs computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

    COLLABORATIVE HARDWARE INTERACTION BY MULTIPLE ENTITIES USING A SHARED QUEUE
    128.
    发明申请
    COLLABORATIVE HARDWARE INTERACTION BY MULTIPLE ENTITIES USING A SHARED QUEUE 审中-公开
    使用共享队列的多个实体的协同硬件交互

    公开(公告)号：US20160117277A1

    公开(公告)日：2016-04-28

    申请号：US14918599

    申请日：2015-10-21

    Applicant: Mellanox Technologies Ltd.

    Inventor： Shachar Raindel ,  Liran Liss

    IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/385 ,  G06F9/546 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

    Abstract: A method for interaction by a central processing unit (CPU) and peripheral devices in a computer includes allocating, in a memory, a work queue for controlling a first peripheral device of the computer. The CPU prepares a work request for insertion in the allocated work queue, the work request specifying an operation for execution by the first peripheral device. A second peripheral device of the computer submits an instruction to the first peripheral device to execute the work request that was prepared by the CPU and thereby to perform the operation specified by the work request.

    Abstract translation: 中央处理单元（CPU）和计算机中的外围设备的交互方法包括在存储器中分配用于控制计算机的第一外围设备的工作队列。 CPU准备在分配的工作队列中插入的工作请求，工作请求指定由第一外围设备执行的操作。 计算机的第二外围设备向第一外围设备提交指令以执行由CPU准备的工作请求，从而执行由工作请求指定的操作。

    CONGESTION CONTROL ENFORCEMENT IN A VIRTUALIZED ENVIRONMENT
    129.
    发明申请
    CONGESTION CONTROL ENFORCEMENT IN A VIRTUALIZED ENVIRONMENT 有权
    虚拟环境中的控制强制执行

    公开(公告)号：US20150029853A1

    公开(公告)日：2015-01-29

    申请号：US14338488

    申请日：2014-07-23

    Applicant: Mellanox Technologies Ltd.

    Inventor： Shachar Raindel ,  Noam Bloch ,  Liran Liss ,  Diego Crupnicoff ,  Marina Lipshteyn

    IPC: H04L12/801 ,  H04L12/851 ,  H04L12/931

    CPC classification number: H04L47/127 ,  G06F3/0662 ,  G06F3/0664 ,  H04L12/4633 ,  H04L47/2441 ,  H04L49/50 ,  H04L49/70

    Abstract: In a data network congestion control in a virtualized environment is enforced in packet flows to and from virtual machines in a host. A hypervisor and network interface hardware in the host are trusted components. Enforcement comprises estimating congestion states in the data network attributable to respective packet flows, recognizing a new packet that belongs to one of the data packet flows, and using one or more of the trusted components and to make a determination based on the congestion states that the new packet belongs to a congestion-producing packet flow. A congestion-control policy is applied by one or more of the trusted components to the new packet responsively to the determination.

    Abstract translation: 在数据网络中，虚拟化环境中的拥塞控制在来自主机中的虚拟机的数据包流中实施。 主机中的管理程序和网络接口硬件是可信组件。 执行包括估计可归因于相应分组流的数据网络中的拥塞状态，识别属于数据分组流之一的新分组，以及使用一个或多个可信组件，并基于拥塞状态进行确定 新分组属于产生拥塞的分组流。 响应于该确定，拥塞控制策略由一个或多个可信任组件应用于新分组。

    Sharing address translation between CPU and peripheral devices
    130.
    发明申请
    Sharing address translation between CPU and peripheral devices 有权
    共享CPU和外围设备之间的地址转换

    公开(公告)号：US20140122828A1

    公开(公告)日：2014-05-01

    申请号：US13665946

    申请日：2012-11-01

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Michael Kagan ,  Noam Bloch ,  Liran Liss ,  Shachar Raindel

    IPC: G06F12/10

    CPC classification number: G06F12/1081

    Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

    Abstract translation: 一种用于存储器访问的方法包括在主机操作系统在中央处理单元（CPU）上运行的主机操作系统的控制下维护主机存储器，用于由CPU执行的多个进程的各自的地址转换表。 在外围设备中接收与给定进程相关联的工作项，在主机存储器中具有相应的地址转换表，并指定虚拟存储器地址时，外围设备将虚拟存储器地址转换为物理存储器地址 通过访问主机存储器中给定进程的相应地址转换表。 通过访问主机存储器中的物理存储器地址上的数据，在外围设备中执行工作项。

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