公开(公告)号：US11929139B2

公开(公告)日：2024-03-12

申请号：US17718200

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G11C5/02 ,  G11C5/04 ,  G11C29/50

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C29/50004 ,  G11C29/50012 ,  G11C2029/5002 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Methods of optimizing the placement of memories in a memory device including a substrate and an electrical component, and associated devices and systems, are disclosed herein. A representative method includes first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. The method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. The first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. The method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.

公开(公告)号：US11887649B2

公开(公告)日：2024-01-30

申请号：US17387428

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer

IPC: G11C11/40 ,  G11C11/406

CPC classification number: G11C11/406

Abstract: Methods of operating a number of memory devices are disclosed. A method may include receiving, at each of a number of memory devices, a refresh command. The method may also include refreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, wherein a count of a refresh address counter of at least one memory device of the number of memory devices is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. Related systems and memory modules are also described.

公开(公告)号：US11829366B2

公开(公告)日：2023-11-28

申请号：US17819793

申请日：2022-08-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Libo Wang ,  Di Wu ,  James S. Rehmeyer ,  Anthony D. Veches

IPC: G06F16/2455 ,  G11C11/407 ,  G11C11/4096 ,  G11C11/54 ,  G11C7/10

CPC classification number: G06F16/24558 ,  G11C11/407 ,  G11C7/1006 ,  G11C7/1063 ,  G11C11/4096 ,  G11C11/54

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

公开(公告)号：US11776612B2

公开(公告)日：2023-10-03

申请号：US17545966

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

IPC: G11C11/406 ,  G06F11/30

CPC classification number: G11C11/40626 ,  G06F11/3037 ,  G06F11/3058 ,  G11C11/40607 ,  G11C11/40622

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

公开(公告)号：US20230026202A1

公开(公告)日：2023-01-26

申请号：US17381057

申请日：2021-07-20

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Lawrence D. Smith ,  James S. Rehmeyer

IPC: G11C7/22 ,  G11C7/10 ,  G11C17/16

Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

公开(公告)号：US20220375509A1

公开(公告)日：2022-11-24

申请号：US17882894

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  David R. Brown

IPC: G11C11/406 ,  G11C29/52

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

公开(公告)号：US11488685B2

公开(公告)日：2022-11-01

申请号：US17308448

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt ,  George Raad ,  Seth Eichmeyer ,  Dean Gans

IPC: G11C29/00 ,  G11C17/16 ,  G11C29/02 ,  G11C29/18

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

公开(公告)号：US11450388B2

公开(公告)日：2022-09-20

申请号：US17158490

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer

IPC: G11C16/10 ,  G11C16/30 ,  G11C7/10 ,  G11C16/32 ,  G11C16/34 ,  G11C16/26

Abstract: Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate under two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimum timing and/or voltage conditions across multiple operating voltage levels. Consequently, multiple sets of timing and/or voltage conditions can be identified depending on the operating voltage levels, which can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate with the optimum timing and/or voltage conditions that has been predetermined for the semiconductor device operating under the operating voltage level.

公开(公告)号：US11417411B2

公开(公告)日：2022-08-16

申请号：US17089394

申请日：2020-11-04

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Yoshinori Fujiwara

IPC: G11C29/44 ,  G11C11/408

Abstract: A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.

公开(公告)号：US11341038B2

公开(公告)日：2022-05-24

申请号：US16808607

申请日：2020-03-04

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Timothy B. Cowles

IPC: G06F12/02 ,  G06F3/06 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C7/24 ,  G11C7/06

Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.