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    TWO-TIER DEFECT SCAN MANAGEMENT
    121.
    发明申请
    TWO-TIER DEFECT SCAN MANAGEMENT 有权

    公开(公告)号：US20240402922A1

    公开(公告)日：2024-12-05

    申请号：US18806444

    申请日：2024-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

    IPC: G06F3/06

    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

    STORING PARITY DURING REFRESH OPERATIONS
    122.
    发明公开
    STORING PARITY DURING REFRESH OPERATIONS 审中-公开

    公开(公告)号：US20240354032A1

    公开(公告)日：2024-10-24

    申请号：US18649803

    申请日：2024-04-29

    Applicant: Micron Technology, Inc.

    Inventor： Reshmi Basu ,  Jonathan S. Parry

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

    Redundant array management techniques
    123.
    发明授权
    Redundant array management techniques 有权

    公开(公告)号：US12111724B2

    公开(公告)日：2024-10-08

    申请号：US17648395

    申请日：2022-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1076

    Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

    TOPOLOGY-BASED RETIREMENT IN A MEMORY SYSTEM
    125.
    发明公开
    TOPOLOGY-BASED RETIREMENT IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240290411A1

    公开(公告)日：2024-08-29

    申请号：US18597454

    申请日：2024-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Chun S. Yeung ,  Deping He ,  Jonathan S. Parry

    IPC: G11C29/42 ,  G11C7/04 ,  G11C29/12 ,  G11C29/44

    CPC classification number: G11C29/42 ,  G11C7/04 ,  G11C29/1201 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

    Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

    ORDERING ENTRIES OF AN INPUT COMMAND QUEUE
    126.
    发明公开
    ORDERING ENTRIES OF AN INPUT COMMAND QUEUE 审中-公开

    公开(公告)号：US20240289052A1

    公开(公告)日：2024-08-29

    申请号：US18442936

    申请日：2024-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan S. Parry ,  David Aaron Palmer ,  Reshmi Basu

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0683

    Abstract: Methods, systems, and devices for ordering entries of an input command queue are described. A memory system may include an interface (e.g., a host interface) that includes a queue (e.g., an input command queue). The host interface may receive commands from a host system, and the commands may be inserted into the input command queue in an order they are received. In some examples, the memory system may determine a range of logical block addresses (LBAs) associated with one or more entries in the input command queue. The memory system may order (e.g., reorder) the commands such that the respective LBA ranges are contiguous.

    POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS
    127.
    发明公开
    POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS 审中-公开

    公开(公告)号：US20240288924A1

    公开(公告)日：2024-08-29

    申请号：US18443955

    申请日：2024-02-16

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan S. Parry ,  Giuseppe Cariello

    IPC: G11C16/30

    CPC classification number: G06F1/3225 ,  G06F11/3062

    Abstract: Methods, systems, and devices for power arbitration for systems of electronic components are described. A system may include a power source, a signaling conductor coupled with a voltage source, and a set of electronic components. One or more of the electronic components may include respective circuitry coupled with the power source and a respective switching component (e.g., a transistor) coupled with the signaling conductor. In some implementations, an electronic component of the set may be configured to determine an operation of its respective circuitry that is associated with a power consumption from the power source. Based on such a determination, the electronic component may switch its respective switching component in accordance with an identifier associated with the electronic component, and determine whether to perform the operation based on monitoring a signal level of the signaling conductor during the switching.

    PARTITIONED TRANSFERRING FOR WRITE BOOSTER
    128.
    发明公开
    PARTITIONED TRANSFERRING FOR WRITE BOOSTER 审中-公开

    公开(公告)号：US20240241665A1

    公开(公告)日：2024-07-18

    申请号：US18540448

    申请日：2023-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Deping He ,  Jonathan S. Parry

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for partitioned transferring for write booster are described. Techniques are described for a memory system to transfer data from a buffer associated with a write booster mode to higher-density blocks of the memory system based on a type of the data stored in the buffer. A first type of data may be transferred from the buffer to the higher-density blocks before a second type of data may be transferred from the buffer to the higher-density blocks. Prioritizing the transfer of data from the buffer to the higher-density block based on the type of data may reduce a write amplification associated with the memory system.

    Techniques for retiring blocks of a memory system
    129.
    发明授权
    Techniques for retiring blocks of a memory system 有权

    公开(公告)号：US12002531B2

    公开(公告)日：2024-06-04

    申请号：US17648396

    申请日：2022-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

    IPC: G11C29/42 ,  G06F11/07 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

    CPC classification number: G11C29/42 ,  G06F11/076 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

    Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

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