公开(公告)号：US11088169B2

公开(公告)日：2021-08-10

申请号：US16937516

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L21/768 ,  H01L21/02 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/762

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11081495B2

公开(公告)日：2021-08-03

申请号：US16438334

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L29/76 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US10978386B2

公开(公告)日：2021-04-13

申请号：US15133121

申请日：2016-04-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

公开(公告)号：US10903220B2

公开(公告)日：2021-01-26

申请号：US16578042

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

公开(公告)号：US20200279999A1

公开(公告)日：2020-09-03

申请号：US16876693

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/033 ,  H01L21/768 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

公开(公告)号：US10685878B2

公开(公告)日：2020-06-16

申请号：US14563953

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US20200013798A1

公开(公告)日：2020-01-09

申请号：US16439278

申请日：2019-06-12

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/762 ,  H01L27/11556 ,  H01L21/768 ,  H01L29/06

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10446577B1

公开(公告)日：2019-10-15

申请号：US16029144

申请日：2018-07-06

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/02

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10446571B2

公开(公告)日：2019-10-15

申请号：US15170114

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H01L27/11582 ,  H01L27/105 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

公开(公告)号：US10388665B1

公开(公告)日：2019-08-20

申请号：US15992959

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.