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    Novel metal-gate electrode for CMOS transistor applications
    121.
    发明申请
    Novel metal-gate electrode for CMOS transistor applications 有权

    公开(公告)号：US20060017122A1

    公开(公告)日：2006-01-26

    申请号：US11231437

    申请日：2005-09-20

    申请人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

    发明人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

    摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

    Metal-gate electrode for CMOS transistor applications
    123.
    发明授权
    Metal-gate electrode for CMOS transistor applications 有权
    用于CMOS晶体管应用的金属栅电极

    公开(公告)号：US06696345B2

    公开(公告)日：2004-02-24

    申请号：US10041539

    申请日：2002-01-07

    申请人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

    发明人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

    IPC分类号： H01R424

    CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

    摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

    摘要翻译： 描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。 栅电极结构具有三层金属栅电极和多晶硅层。 第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。 第二金属层用于设定栅电极结构的功函数。 第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。制造栅极电极结构的方法包括形成足够厚的三个金属层，以使得每个层提供屏障和所述功能设定功能 而且还足够薄以使得可以进行随后的湿蚀刻而没有金属层的过度底切。 在注入和退火工艺期间，多晶硅层用作金属层上的保护掩模，以保护底层硅衬底与植入过程中使用的掺杂剂相互作用。

    Metalgate electrode for PMOS transistor
    124.
    发明授权
    Metalgate electrode for PMOS transistor 有权
    用于PMOS晶体管的金属栅电极

    公开(公告)号：US07936025B2

    公开(公告)日：2011-05-03

    申请号：US11231437

    申请日：2005-09-20

    申请人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

    发明人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

    IPC分类号： H01L29/78

    CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

    摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.

    摘要翻译： 描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。 栅电极结构具有三层金属栅电极和多晶硅层。 第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。 第二金属层用于设定栅电极结构的功函数。 第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。