公开(公告)号：US20250045157A1

公开(公告)日：2025-02-06

申请号：US18795992

申请日：2024-08-06

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F11/10 ,  G06F11/07 ,  G11C7/10

Abstract: Methods, systems, and devices for memory operations are described. A read command may be received at a memory device from a host device. As part of an error control operation, a first set of error control bits may be generated for the set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation may be determined. Based on determining the failure of the matching operation, a second set of error control bits that is different than the first set of error control bits may be transmitted to the host device. The second set of error control bits may indicate that the matching operation failed at the memory device.

公开(公告)号：US20240372566A1

公开(公告)日：2024-11-07

申请号：US18639692

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: H03M13/15

Abstract: Methods, systems, and devices for selective modes for error control are described. A memory system may implement an error control engine supporting error correction operations and error detection operations. The error control engine may switch between an error correction mode and an error detection mode. The error control engine may receive data and error control information, generate additional error control information, and compare the received and generated error control information to detect one or more errors in the data. In some examples, the error control engine may be configured to operate in the error correction mode, and the error control engine may correct single-bit errors in the data. In other examples, the error control engine may be configured to operate in the error detection mode, and the error control engine may detect errors in the data and transmit an indication of the errors.

公开(公告)号：US12051477B2

公开(公告)日：2024-07-30

申请号：US17815747

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/46 ,  G11C7/10 ,  G11C29/12

CPC classification number: G11C29/46 ,  G11C7/1063 ,  G11C29/1201

Abstract: Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.

公开(公告)号：US20240250699A1

公开(公告)日：2024-07-25

申请号：US18594795

申请日：2024-03-04

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  G06F11/07 ,  H03M13/00

CPC classification number: H03M13/159 ,  G06F11/073 ,  G06F11/0787 ,  H03M13/611

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

公开(公告)号：US20240220361A1

公开(公告)日：2024-07-04

申请号：US18608460

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/0793

Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.

公开(公告)号：US12014792B2

公开(公告)日：2024-06-18

申请号：US18108302

申请日：2023-02-10

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G06F12/02 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G06F12/0238 ,  G11C29/12005 ,  G11C29/12015 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C2207/2254

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US12001305B2

公开(公告)日：2024-06-04

申请号：US17820128

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F11/27 ,  G06F9/50

CPC classification number: G06F11/27 ,  G06F9/5044

Abstract: Implementations described herein relate to resource allocation for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify one or more memory resources of the memory device, based on reading the one or more bits, that are to be used for performing the memory built-in self-test. The one or more memory resources of the memory device may be addressable memory resources configured for performing standard memory operations of the memory device. The memory device may perform the memory built-in self-test for the memory device using the one or more memory resources of the memory device.

公开(公告)号：US20240126447A1

公开(公告)日：2024-04-18

申请号：US17964706

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

Abstract: Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.

公开(公告)号：US11942966B2

公开(公告)日：2024-03-26

申请号：US17816320

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/00 ,  G06F11/07 ,  H03M13/15

CPC classification number: H03M13/159 ,  G06F11/073 ,  G06F11/0787 ,  H03M13/611

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

公开(公告)号：US11894085B2

公开(公告)日：2024-02-06

申请号：US17807303

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/12 ,  G06F11/10

CPC classification number: G11C29/12 ,  G06F11/1044

Abstract: Implementations described herein relate to memory section selection for a memory built-in self-test. A memory device may read a first set of bits stored in a test control mode register. The memory device may identify a test mode, for performing a memory built-in self-test, based on the first set of bits. The memory device may read a second set of bits stored in a section identifier mode register. The memory device may identify one or more memory sections of the memory device, for which the memory built-in self-test is to be performed, based on the second set of bits. The one or more memory sections may be a subset of a plurality of memory sections into which the memory device is divided. The memory device may perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode.