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公开(公告)号：US07747736B2
公开(公告)日：2010-06-29
申请号：US11422239
申请日：2006-06-05
申请人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
发明人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
IPC分类号： G06F3/06 , G06F7/04 , G06F9/44 , G06F15/16 , G06F15/173 , G06F15/177 , G06F17/00 , G06F17/30 , G06F17/50 , H04L29/06
CPC分类号： G06Q10/06 , G06Q10/063
摘要： A computer implemented method, data processing system, and computer program product for nominating rules or policies for promotion through a policy hierarchy. An administrator at any level in a policy hierarchy may create a rule or policy. The administrator may then nominate the rule or policy for inclusion in a next higher level in the policy hierarchy. The rule or policy is evaluated at the next higher level. Responsive to an approval of the next higher level to include the rule or policy in the jurisdiction of the next higher level, the rule of policy is provided to all users under the jurisdiction. The nominating, evaluating, and providing steps may then be repeated for each higher level in the policy hierarchy.
摘要翻译： 计算机实现的方法，数据处理系统和计算机程序产品，用于通过策略层次结构提名规则或策略。 策略层次结构中任何级别的管理员可能会创建规则或策略。 然后，管理员可以提名规则或策略以包含在策略层次结构中的下一个较高级别中。 规则或策略在下一个更高级别进行评估。 响应上一级批准，将规则或者政策纳入下一级管辖范围，向所有管辖的用户提供政策规则。 然后可以在策略层次结构中的每个较高级别重复提名，评估和提供步骤。
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122.发明申请Method, System and Program Product for Address Translation Through an Intermediate Address Space 有权通过中间地址空间进行地址转换的方法，系统和程序产品公开(公告)号：US20090113164A1
公开(公告)日：2009-04-30
申请号：US11928125
申请日：2007-10-30
IPC分类号： G06F9/26
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译： 在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。 使用中间地址访问高速缓冲存储器。 响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。 使用实际地址访问系统内存。
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公开(公告)号：US20090063826A1
公开(公告)日：2009-03-05
申请号：US12264764
申请日：2008-11-04
IPC分类号： G06F9/30
CPC分类号： G06F9/52
摘要： A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.
摘要翻译： 一种用于在多处理器计算机系统中有效地处理高争用锁定的方法和计算机系统。 系统中的至少一些处理器被组织成层次结构，并响应层次结构处理可中断的锁。 该方法利用获取锁的两种替代方法，包括条件锁获取原语和无条件锁获取原语，以及用于从特定处理器释放锁的无条件锁释放原语。 为了防止请求锁获取的处理器和释放锁的处理器之间的比赛，利用释放标志。 此外，为了确保使用无条件锁定获取原语的处理器被授予锁定，则利用切换标志。
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公开(公告)号：US07500036B2
公开(公告)日：2009-03-03
申请号：US09753062
申请日：2000-12-28
IPC分类号： G06F12/00
CPC分类号： G06F9/52
摘要： A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy, and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.
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125.发明授权Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system 失效动态调整预取距离，以便在处理系统中实现即时预取公开(公告)号：US07487297B2
公开(公告)日：2009-02-03
申请号：US11422459
申请日：2006-06-06
IPC分类号： G06F13/00
CPC分类号： G06F12/0862
摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
摘要翻译： 一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。 该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求） 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。
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公开(公告)号：US20080016330A1
公开(公告)日：2008-01-17
申请号：US11457178
申请日：2006-07-13
IPC分类号： G06F9/44
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0897 , G06F2212/6026
摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.
摘要翻译： 一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。 在预取引擎（或与其相关联）中提供了多个（简单）历史表。 多个表中的每一个用于检测不同的访问模式。 这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。 当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。 以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。
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公开(公告)号：US20070282986A1
公开(公告)日：2007-12-06
申请号：US11422239
申请日：2006-06-05
申请人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
发明人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
IPC分类号： G06F15/173
CPC分类号： G06Q10/06 , G06Q10/063
摘要： A computer implemented method, data processing system, and computer program product for nominating rules or policies for promotion through a policy hierarchy. An administrator at any level in a policy hierarchy may create a rule or policy. The administrator may then nominate the rule or policy for inclusion in a next higher level in the policy hierarchy. The rule or policy is evaluated at the next higher level. Responsive to an approval of the next higher level to include the rule or policy in the jurisdiction of the next higher level, the rule of policy is provided to all users under the jurisdiction. The nominating, evaluating, and providing steps may then be repeated for each higher level in the policy hierarchy.
摘要翻译： 计算机实现的方法，数据处理系统和计算机程序产品，用于通过策略层次结构提名规则或策略。 策略层次结构中任何级别的管理员可能会创建规则或策略。 然后，管理员可以提名规则或策略以包含在策略层次结构中的下一个较高级别中。 规则或策略在下一个更高级别进行评估。 响应上一级批准，将规则或者政策纳入下一级管辖范围，向所有管辖的用户提供政策规则。 然后可以在策略层次结构中的每个较高级别重复提名，评估和提供步骤。
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公开(公告)号：US20070067604A1
公开(公告)日：2007-03-22
申请号：US11551168
申请日：2006-10-19
IPC分类号： G06F12/00
CPC分类号： G06F12/1045
摘要： A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation look aside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.
摘要翻译： 将虚拟存储器分配给数据处理系统中的物理存储器的方法为新的页面映射分配一组连续的物理存储器页面，指示存储器控制器根据新的页面映射移动虚拟存储器页面，然后允许访问 虚拟内存页面使用新页面映射，而内存控制器仍将虚拟内存页面复制到物理内存页面集合。 存储器控制器可以使用临时存储旧页面地址和新页面地址的条目的映射表，并且对于每个条目的拷贝完成，释放条目。 在存储器控制器完成内存页复制之前，处理器核心中的缓冲区（TLB）条目将被更新为新页面地址。 本发明可以扩展到非均匀存储器阵列（NUMA）系统。 对于具有缓存内存的系统，可以通过根据新页面映射修改其地址标签来更新受页面移动影响的任何缓存条目。 该标签修改可能被限制在脏相关性状态下的高速缓存条目。 高速缓存可以根据修改后的地址标签的改变的一致性类别进一步重新定位缓存条目。
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129.发明授权Method and memory controller for adaptive row management within a memory subsystem 失效方法和内存控制器，用于存储器子系统内的自适应行管理公开(公告)号：US07082514B2
公开(公告)日：2006-07-25
申请号：US10666814
申请日：2003-09-18
IPC分类号： G06F12/00
CPC分类号： G06F13/1631 , G06F12/0215
摘要： A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the memory subsystem in conformity with measured metrics to reduce the average latency of the memory subsystem. Counters provided within the memory controller track the number of consecutive row accesses and optionally the number of total accesses over a measurement interval. The number of counted consecutive row accesses can be used to control the closing of rows for subsequent accesses, reducing memory latency. The count may be validated using a second counter or storage for improved accuracy and alternatively the row close count may be set via program or logic control in conformity with a count of consecutive row hits in ratio with a total access count. The control of row closure may be performed by a mode selection between always closing a row (non-page mode) or always holding a row open (page mode) or by intelligently closing rows after a count interval (row hold count) determined from the consecutive row access measurements. The logic and counters may be incorporated within the memory controller or within the memory devices and the controller/memory devices may provide I/O ports or memory locations for reading the count values and/or setting a row management mode or row hold count.
摘要翻译： 用于存储器子系统内的自适应行管理的方法和存储器控制器提供用于评估行访问行为的度量，并且根据所测量的度量来动态调整存储器子系统的行管理策略，以减少存储器子系统的平均等待时间。 存储器控制器内提供的计数器跟踪连续行访问的次数，以及可选的测量间隔内总访问次数。 可以使用计数的连续行访问次数来控制后续访问的行关闭，从而减少内存延迟。 可以使用第二计数器或存储器来对计数进行验证，以提高精确度，或者可以通过程序或逻辑控制来设置行关闭计数，这与根据总接入计数的比率的连续行命中的计数一致。 行闭合的控制可以通过总是关闭行（非页面模式）或总是保持行打开（页面模式）之间的模式选择来执行，或者通过在从所述第一模式确定的计数间隔（行保持计数）之后智能地关闭行来执行 连续行访问测量。 逻辑和计数器可以并入存储器控制器内或存储器件内，并且控制器/存储器设备可以提供用于读取计数值的I / O端口或存储器位置和/或设置行管理模式或行保持计数。
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130.发明授权公开(公告)号：US07080214B2
公开(公告)日：2006-07-18
申请号：US10687261
申请日：2003-10-16
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/0817
摘要： A multiprocessor system includes a plurality of data processing nodes. Each node has a processor coupled to a system memory, a cache memory, and a cache directory. The cache directory contains cache coherency information for a predetermined range of system memory addresses. An interconnection enables the nodes to exchange messages. A node initiating a function shipping request identifies an intermediate destination directory based on a list of the function's operands and sends a message indicating the function and its corresponding operands to the identified destination directory. The destination cache directory determines a target node based, at least in part, on its cache coherency status information to reduce memory access latency by selecting a target node where all or some of the operands are valid in the local cache memory. The destination directory then ships the function to the target node over the interconnection.
摘要翻译： 多处理器系统包括多个数据处理节点。 每个节点具有耦合到系统存储器，高速缓存存储器和高速缓存目录的处理器。 缓存目录包含用于系统存储器地址的预定范围的高速缓存一致性信息。 互连使得节点能够交换消息。 启动功能运送请求的节点基于功能的操作数的列表来识别中间目的地目录，并将指示该功能及其对应的操作数的消息发送到所识别的目的地目录。 目的地缓存目录至少部分地基于其高速缓存一致性状态信息来确定目标节点，以通过选择其中全部或某些操作数在本地高速缓冲存储器中有效的目标节点来减少存储器访问等待时间。 目的地目录然后通过互连将功能发送到目标节点。
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