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公开(公告)号：US06737222B2
公开(公告)日：2004-05-18
申请号：US09884834
申请日：2001-06-19
IPC分类号： G03F700
CPC分类号： H01L21/76829 , G03F7/0035 , G03F7/095 , H01L21/0274 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L2221/1031
摘要： A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
摘要翻译： 利用多层光刻胶形成接触孔和/或使用双镶嵌工艺的导体的方法包括利用层状光致抗蚀剂。 可以在单个沉积步骤中或在两级沉积步骤中形成导电线中的接触。 图像层可以保留为互连结构的一部分，或者通过抛光技术去除。 该方法可用于设置在集成电路的衬底上的任何导电结构。
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公开(公告)号：US06686270B1
公开(公告)日：2004-02-03
申请号：US10212983
申请日：2002-08-05
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76813 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.
摘要翻译： 本发明的一个方面涉及一种双镶嵌加工方法，包括在绝缘结构中形成多个通孔，该绝缘结构包含单层电介质材料; 并且（i）在所述绝缘结构中形成多个沟槽，每个沟槽沿着一组通孔开口的基本直线定位，以及（ii）使用散射测量系统监测沟槽的形成以确定沟槽深度，并且终止 当获得所需的沟槽深度时形成沟槽。
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123.发明授权公开(公告)号：US06654659B1
公开(公告)日：2003-11-25
申请号：US10178084
申请日：2002-06-24
IPC分类号： G06F1900
CPC分类号： H01L21/67253 , H01L21/67063 , H01L22/20
摘要： One aspect of the present invention relates to a feedback-driven, closed loop system/method for obtaining consistently formed semiconductor structures. The system/method involves controlling the progression of a lithography process such as a deposition or etching process. The system employs one or more piezoelectric sensors, such as quartz crystal sensors, integrated on a wafer. During the lithography process, the sensors produce frequency data which is analyzed and communicated to a lithography process controller in order to modulate one or more process parameters and/or one or more process components. The frequency data indicates the progression of the lithography process and facilitates determining whether the parameters/components need correction to obtain structures which are consistent throughout the wafer and from wafer to wafer. Data generated by each sensor located at an area on the wafer may be cross-referenced with data from other sensors on the wafer and with data from other wafers to ensure uniformity and consistency among the wafers.
摘要翻译： 本发明的一个方面涉及一种用于获得一致形成的半导体结构的反馈驱动的闭环系统/方法。 该系统/方法涉及控制诸如沉积或蚀刻工艺的光刻工艺的进展。 该系统采用集成在晶片上的一个或多个压电传感器，例如石英晶体传感器。 在光刻过程期间，传感器产生频率数据，其被分析并传送到光刻过程控制器，以便调制一个或多个过程参数和/或一个或多个过程组件。 频率数据指示光刻过程的进展，并且有助于确定参数/组件是否需要校正以获得在整个晶片和晶片与晶片之间一致的结构。 由位于晶片上的每个传感器生成的数据可以与来自晶片上的其他传感器的数据和来自其他晶片的数据进行交叉参考，以确保晶片之间的均匀性和一致性。
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公开(公告)号：US06624642B1
公开(公告)日：2003-09-23
申请号：US10016252
申请日：2001-12-10
IPC分类号： G01R2700
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译： 公开了一种包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层，以及至少一个嵌入在晶片中和晶片中的至少一个的电传感器，以促进金属层在其进行时的实时监测 减色金属化工艺。 该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动 从电传感器检测和接收，用于实时监测减色金属化处理。
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公开(公告)号：US06589711B1
公开(公告)日：2003-07-08
申请号：US09824696
申请日：2001-04-04
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.
摘要翻译： 提供了在第一层中制作双重嵌入通孔的方法。 第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。 该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成双层抗蚀剂。 双层抗蚀剂包括底部抗反射涂层（BARC）上方的成像层。 成像层选择性地暴露于辐射，使得在通过BARC的上部的第一开口中没有辐射到达BARC的下部。 双层抗蚀剂被图案化，并且使用图案化双层抗蚀剂作为掩模，形成与第一开口连通的第二开口，例如沟槽。
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126.发明授权公开(公告)号：US06440640B1
公开(公告)日：2002-08-27
申请号：US09703092
申请日：2000-10-31
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： G03C500
CPC分类号： H01L21/76816 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/32139
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在介电层上形成过渡金属层。 在过渡金属层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以形成通孔图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到过渡金属层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的过渡金属层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，过渡金属层用作硬掩模，以通过蚀刻介电层的部分形成与通孔图案相对应的接触孔。
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127.发明授权公开(公告)号：US06423475B1
公开(公告)日：2002-07-23
申请号：US09266367
申请日：1999-03-11
IPC分类号： G03C500
CPC分类号： H01L21/32139
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a photoresist over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the photoresist having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the photoresist, the sidewall film having a vertical portion adjacent the sidewall of the photoresist and a horizontal portion in areas not adjacent the sidewall of the photoresist; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the photoresist exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化光致抗蚀剂，其中所述导电膜的第二部分被暴露，所述光致抗蚀剂在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述光致抗蚀剂上沉积侧壁膜，所述侧壁膜具有邻近所述光致抗蚀剂的侧壁的垂直部分和在不邻近所述光致抗蚀剂的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的光致抗蚀剂; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。
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公开(公告)号：US06403456B1
公开(公告)日：2002-06-11
申请号：US09643611
申请日：2000-08-22
IPC分类号： H01L2128
CPC分类号： H01L29/42376 , H01L21/28114 , H01L21/28123 , H01L21/76802
摘要： A method for fabricating a T-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. A photoresist layer is formed over the second sacrificial layer. An opening is formed in the photoresist layer. An opening is then formed in the second sacrificial layer beneath the opening in the photoresist layer. The opening is then expanded in the photoresist layer to expose portions of the top surface of the second sacrificial layer around the opening in the second sacrificial layer. The opening is extended in the second sacrificial layer through the first sacrificial layer and the opening is expanded in the second sacrificial layer to form a T-shaped opening in the first and second sacrificial layers. The photoresist layer is removed and the T-shaped opening is filled with a conductive material.
摘要翻译： 提供了一种制造T型栅结构的方法。 该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。 在第二牺牲层上形成光致抗蚀剂层。 在光致抗蚀剂层中形成开口。 然后在光致抗蚀剂层中的开口下方的第二牺牲层中形成开口。 然后在光致抗蚀剂层中扩展开口，以暴露第二牺牲层的顶表面的部分围绕第二牺牲层中的开口。 所述开口在所述第二牺牲层中延伸穿过所述第一牺牲层，并且所述开口在所述第二牺牲层中膨胀以在所述第一和第二牺牲层中形成T形开口。 去除光致抗蚀剂层，并用导电材料填充T形开口。
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129.发明授权Sub-lithographic contacts and vias through pattern, CVD and etch back processing 有权亚光刻触点和通孔，通过图案，CVD和回蚀处理公开(公告)号：US06399284B1
公开(公告)日：2002-06-04
申请号：US09336619
申请日：1999-06-18
申请人： Christopher F. Lyons
发明人： Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： H01L21/76816 , H01L21/76831
摘要： In one embodiment, the present invention relates to a method of forming a sub-lithographic via or contact, involving the steps of providing a substrate comprising a conductor having a width of about 0.25 &mgr;m or less over a portion of the substrate and an insulating film over the conductor and the substrate; etching a preliminary via in the insulating film over the conductor, the preliminary via defined by sidewalls in the insulating film; depositing a CVD layer over the substrate, the insulating film, and the conductor, the CVD layer having a vertical portion adjacent the sidewalls of the insulating film and a horizontal portion in areas not adjacent the sidewalls of the insulating film; removing the horizontal portion of the CVD layer thereby forming the sub-lithographic via over the conductor, and depositing a conductive material into the sub-lithographic via to form a sub-lithographic contact, the sub-lithographic via and/or sub-lithographic contact having a width of less than about 0.25 &mgr;m.
摘要翻译： 在一个实施例中，本发明涉及一种形成亚光刻通孔或接触件的方法，包括以下步骤：提供包括在衬底的一部分上具有约0.25μm或更小的宽度的导体的衬底和绝缘膜 在导体和基板上; 在导体上蚀刻绝缘膜中的预备通孔，由绝缘膜中的侧壁限定的预备通孔; 在衬底，绝缘膜和导体上沉积CVD层，CVD层具有与绝缘膜的侧壁相邻的垂直部分和不邻近绝缘膜的侧壁的水平部分; 去除CVD层的水平部分，从而在导体上形成亚光刻通孔，并将导电材料沉积到亚光刻通孔中以形成亚光刻接触，子光刻通孔和/或亚光刻接触 具有小于约0.25μm的宽度。
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130.发明授权公开(公告)号：US06350559B1
公开(公告)日：2002-02-26
申请号：US09398642
申请日：1999-09-17
IPC分类号： G03F700
CPC分类号： H01L21/312 , G03F7/168
摘要： In one embodiment, the present invention relates to a method of forming a thin photoresist layer having a low defect density, involving the steps of depositing a photoresist layer having a thickness from greater than about 0.5 &mgr;m to about 2 &mgr;m on a semiconductor substrate; and removing at least a portion of the photoresist layer to provide the thin photoresist layer having the low defect density and a thickness from about 0.1 &mgr;m to about 0.5 &mgr;m. In another embodiment, the present invention relates to a method of reducing pinhole defects in a thin photoresist layer having a thickness below about 0.5 &mgr;m comprising a photoresist material, involving the steps of depositing a layer of the photoresist material having a thickness greater than about 0.5 &mgr;m; and etching at least a portion of the photoresist material to provide the thin photoresist layer having the thickness below about 0.5 &mgr;m, wherein the thickness of the thin photoresist layer is about 90% or less than the thickness of the layer of the photoresist material.
摘要翻译： 在一个实施方案中，本发明涉及一种形成具有低缺陷密度的薄的光致抗蚀剂层的方法，包括以下步骤：在半导体衬底上沉积厚度大于约0.5μm至约2μm的光致抗蚀剂层; 以及去除所述光致抗蚀剂层的至少一部分以提供具有低缺陷密度和约0.1μm至约0.5μm的厚度的薄光致抗蚀剂层。 在另一个实施方案中，本发明涉及一种减少厚度低于约0.5μm的光致抗蚀剂薄层中的针孔缺陷的方法，该光致抗蚀剂层包括光致抗蚀剂材料，其包括以下步骤：沉积厚度大于约0.5μm的光致抗蚀剂材料层 妈妈 并蚀刻所述光致抗蚀剂材料的至少一部分以提供具有低于约0.5μm厚度的薄的光致抗蚀剂层，其中所述光致抗蚀剂层的厚度为所述光致抗蚀剂材料层的厚度的约90％或更小。
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