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    3D MEMORY ARRAY CONTACT STRUCTURES
    125.
    发明申请
    3D MEMORY ARRAY CONTACT STRUCTURES 有权

    公开(公告)号：US20210408038A1

    公开(公告)日：2021-12-30

    申请号：US17231523

    申请日：2021-04-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Feng-Cheng Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

    Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

    3D Semiconductor Package Including Memory Array
    126.
    发明申请
    3D Semiconductor Package Including Memory Array 有权

    公开(公告)号：US20210407980A1

    公开(公告)日：2021-12-30

    申请号：US17138270

    申请日：2020-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: H01L25/18 ,  H01L29/24 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/1159 ,  H01L27/11597 ,  H01L23/48

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die is bonded to the being structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

    MEMORY DEVICE AND METHOD OF FORMING THE SAME
    127.
    发明申请
    MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210399052A1

    公开(公告)日：2021-12-23

    申请号：US17123925

    申请日：2020-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  G11C7/18 ,  G11C8/14 ,  H01L29/78

    Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

    SEMICONDUCTOR STRUCTURE HAVING MEMORY DEVICE AND METHOD OF FORMING THE SAME
    128.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210398992A1

    公开(公告)日：2021-12-23

    申请号：US17132305

    申请日：2020-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/11502 ,  G11C5/06 ,  G11C11/22 ,  H01L27/11585

    Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

    SELF-ALIGNED CONTACT STRUCTURES
    129.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURES 有权

    公开(公告)号：US20210384316A1

    公开(公告)日：2021-12-09

    申请号：US16895604

    申请日：2020-06-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L21/768

    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

    3D FERROELECTRIC MEMORY
    130.
    发明申请
    3D FERROELECTRIC MEMORY 有权

    公开(公告)号：US20210375932A1

    公开(公告)日：2021-12-02

    申请号：US17113249

    申请日：2020-12-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

    Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

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