公开(公告)号：US12225731B2

公开(公告)日：2025-02-11

申请号：US17818638

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

公开(公告)号：US11716856B2

公开(公告)日：2023-08-01

申请号：US17193331

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Meng-Han Lin ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L21/02 ,  H01L29/24 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/02565 ,  H01L23/5226 ,  H01L29/24 ,  H10B51/30

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

公开(公告)号：US20210408120A1

公开(公告)日：2021-12-30

申请号：US17229395

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Yu Chang ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/24 ,  H01L29/861 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

公开(公告)号：US12256550B2

公开(公告)日：2025-03-18

申请号：US18327439

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Meng-Han Lin ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L21/02 ,  H01L23/522 ,  H01L29/24 ,  H10B51/30

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

公开(公告)号：US20240268128A1

公开(公告)日：2024-08-08

申请号：US18637552

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Yu Chang ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/861 ,  H10B43/20 ,  H10B43/35 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H01L21/02565 ,  H01L21/8221 ,  H01L21/823475 ,  H01L27/0688 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/861 ,  H10B43/20 ,  H10B63/20 ,  H10B63/30 ,  H10N70/011 ,  H10B43/35 ,  H10N70/20

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

公开(公告)号：US11991888B2

公开(公告)日：2024-05-21

申请号：US18343912

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Yu Chang ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/861 ,  H10B43/20 ,  H10N70/00 ,  H10B43/35 ,  H10N70/20

CPC classification number: H10B63/84 ,  H01L21/02565 ,  H01L21/8221 ,  H01L21/823475 ,  H01L27/0688 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/861 ,  H10B43/20 ,  H10B63/20 ,  H10B63/30 ,  H10N70/011 ,  H10B43/35 ,  H10N70/20

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

公开(公告)号：US11974441B2

公开(公告)日：2024-04-30

申请号：US17138152

申请日：2020-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0653 ,  H01L29/0669 ,  H10B51/10

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

公开(公告)号：US11901450B2

公开(公告)日：2024-02-13

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/0234 ,  H01L21/02181 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20230369471A1

公开(公告)日：2023-11-16

申请号：US18358066

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/6684 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/513 ,  H01L29/66795 ,  H01L29/516

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US20230345741A1

公开(公告)日：2023-10-26

申请号：US18343912

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Yu Chang ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B63/00 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/861 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/06 ,  H10B43/20 ,  H10N70/00

CPC classification number: H10B63/84 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02565 ,  H01L29/861 ,  H01L21/823475 ,  H01L21/8221 ,  H01L27/0688 ,  H10B43/20 ,  H10B63/20 ,  H10B63/30 ,  H10N70/011 ,  H10B43/35

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.