公开(公告)号：US11031489B2

公开(公告)日：2021-06-08

申请号：US16142672

申请日：2018-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu

IPC: H01L21/02 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

公开(公告)号：US11011625B2

公开(公告)日：2021-05-18

申请号：US16510554

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20210066294A1

公开(公告)日：2021-03-04

申请号：US16932476

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US10825918B2

公开(公告)日：2020-11-03

申请号：US16260483

申请日：2019-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi-Ning Ju

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.

公开(公告)号：US20200098758A1

公开(公告)日：2020-03-26

申请号：US16279824

申请日：2019-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/11 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

公开(公告)号：US20200098622A1

公开(公告)日：2020-03-26

申请号：US16510554

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20200006531A1

公开(公告)日：2020-01-02

申请号：US16544196

申请日：2019-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/768

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US10388771B1

公开(公告)日：2019-08-20

申请号：US16021344

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US10269914B2

公开(公告)日：2019-04-23

申请号：US15716699

申请日：2017-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Wu ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a first device with a horizontal-gate-all-around configuration, and a second device with a horizontal-gate-all-around configuration. The first device is over the substrate. The second device is over the first device. A channel of the first device is between the substrate and a channel of the second device.

公开(公告)号：US20150054039A1

公开(公告)日：2015-02-26

申请号：US13970790

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Chao Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/76

CPC classification number: H01L29/785 ,  H01L21/76 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.

Abstract translation: 本公开涉及具有外延增强结构的Fin场效应晶体管（FinFET）器件及其相关制造方法。 在一些实施例中，FinFET器件具有半导体衬底，其具有覆盖半导体衬底的多个隔离区域。 在多个隔离区域之间的位置处，多个三维翅片从半导体衬底的顶表面突出。 相应的三维翅片具有向三维翅片引入应变的外延增强结构。 外延增强结构被布置在三维鳍片内的半导体材料上方，位于相邻隔离区域的底部之上超过10纳米的位置。 在这样的位置形成外延增强结构提供足够的结构支撑以避免隔离区域崩溃。