公开(公告)号：US20070210658A1

公开(公告)日：2007-09-13

申请号：US11547923

申请日：2005-04-08

申请人： Takahiro Terauchi ,  Chikahumi Sugai ,  Takeshi Yamazaki ,  Satoru Negishi ,  Hideaki Fujii

发明人： Takahiro Terauchi ,  Chikahumi Sugai ,  Takeshi Yamazaki ,  Satoru Negishi ,  Hideaki Fujii

IPC分类号： H02K11/00 ,  H02K5/00

CPC分类号： H02K5/04 ,  H02K5/225 ,  H02K29/12

摘要： The brushless motor includes: a housing; a stator which is stored and fixed in the housing; a rotor which is rotatably arranged inside the stator; a bracket which is fixed to the housing; a rotation detector which is fixed to the bracket and the housing and detects a rotation position of the rotor; and an engagement device which restrains movement of the bracket along a circumferential direction with respect to the housing.

摘要翻译： 无刷电动机包括：壳体; 定子，其被存储并固定在所述壳体中; 转子，其可旋转地布置在所述定子内; 固定在壳体上的支架; 旋转检测器，其固定到所述支架和所述壳体并检测所述转子的旋转位置; 以及接合装置，其限制支架相对于壳体沿圆周方向的移动。

公开(公告)号：US07233998B2

公开(公告)日：2007-06-19

申请号：US09816004

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US20060270283A1

公开(公告)日：2006-11-30

申请号：US11431548

申请日：2006-05-11

申请人： Takeshi Kumazawa ,  Takeshi Yamazaki ,  Takuni Yoshida

发明人： Takeshi Kumazawa ,  Takeshi Yamazaki ,  Takuni Yoshida

IPC分类号： H01R24/00

CPC分类号： G02B6/3897 ,  G02B6/42

摘要： A photoelectric combined connector includes a first connector and a second connector. The first connector includes a first housing and a first electrical terminal disposed in the first housing. The second connector includes a second housing, a board disposed in the second housing and having a photoelectric conversion unit, and a second electrical terminal disposed in the second housing. The second electrical terminal includes a fitted-in portion into which a part of the board is fitted when the board is attached to the second housing. When the first connector is connected to the second connector, the first electrical terminal of the first connector electrically contacts with the second electrical terminal of the second connector. Through the contact, the first electrical terminal of the first connector electrically contacts with the photoelectric conversion unit of the second connector.

摘要翻译： 光电组合连接器包括第一连接器和第二连接器。 第一连接器包括第一壳体和设置在第一壳体中的第一电气端子。 第二连接器包括第二壳体，设置在第二壳体中并具有光电转换单元的板和设置在第二壳体中的第二电端子。 第二电气端子包括嵌入部分，当板被附接到第二壳体时，其中安装有板的一部分。 当第一连接器连接到第二连接器时，第一连接器的第一电端子与第二连接器的第二电端子电接触。 通过接触，第一连接器的第一电端子与第二连接器的光电转换单元电接触。

公开(公告)号：US20060209121A1

公开(公告)日：2006-09-21

申请号：US11370822

申请日：2006-03-08

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： B41J2/165

CPC分类号： B41J2/16508 ,  B41J2/16532

摘要： An inkjet recording apparatus, including: a printing head having a plurality of nozzle holes which emit ink; and a capping device to collect ink ejected from the nozzle hole by covering the nozzle hole of the printing head, wherein the capping device has an interconnected cell type porous elastic member to contact with the surface of nozzle member at a peripheral area of the nozzle hole, a recessed area not to block up the nozzle hole of the printing head, on a surface of porous elastic member which contacts with the surface of nozzle member, a base member to hose the porous elastic member, and a suction device communicated to the recessed area of the porous elastic member to suction ink form the nozzle hole of the printing head.

摘要翻译： 一种喷墨记录装置，包括：具有多个排出墨水的喷嘴孔的打印头; 以及封盖装置，通过覆盖打印头的喷嘴孔来收集从喷嘴孔喷射的墨，其中封盖装置具有互连的电池型多孔弹性构件，以在喷嘴孔的周边区域与喷嘴构件的表面接触 在与喷嘴构件的表面接触的多孔弹性构件的表面上形成不堵塞打印头的喷嘴孔的凹陷区域，用于软管多孔弹性构件的基座构件和连通到凹部的抽吸装置 多孔弹性构件到吸墨的区域形成打印头的喷嘴孔。

公开(公告)号：US07099975B2

公开(公告)日：2006-08-29

申请号：US10730952

申请日：2003-12-09

申请人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

发明人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

IPC分类号： G06F12/00

CPC分类号： G06F13/3625

摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

摘要翻译： 一种改进的资源仲裁方法和装置。 定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器（ARC），通过该资源访问资源。 在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。 如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

公开(公告)号：US20060129786A1

公开(公告)日：2006-06-15

申请号：US11011784

申请日：2004-12-14

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/10 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/651 ,  G06F2212/652

摘要： Methods and apparatus provide for using a first portion of an external address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory; using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; and using a second portion of the external address as a pointer to one of the entries in the page table to obtain an at least partially translated physical address into the memory for the external address.

摘要翻译： 方法和装置提供使用外部地址的第一部分作为指针来选择段表中的多个条目中的一个，段表的每个条目表示存储器的不同段; 使用片段表的所选条目的至少一部分作为对页表中的多个条目中的一个或多个的引用，页表中的每个条目包括存储器中的物理地址的至少一部分并且属于 到表示存储器的所选段中的页面的一组条目; 以及使用外部地址的第二部分作为指向页表中的一个条目的指针，以获得用于外部地址的存储器中的至少部分转换的物理地址。

公开(公告)号：US20060092957A1

公开(公告)日：2006-05-04

申请号：US11250246

申请日：2005-10-14

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： H04L12/28

CPC分类号： G06F12/0815 ,  G06F12/0835

摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

摘要翻译： 方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

公开(公告)号：US20050251655A1

公开(公告)日：2005-11-10

申请号：US11110307

申请日：2005-04-20

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/00 ,  G06F15/80

CPC分类号： G06F9/30101 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3887

摘要： A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The method includes a) detecting a plurality of sequences of instructions adapted for parallel execution from instructions being provided to the processor, wherein each sequence is adapted for execution by a subset of the plurality of execution units and b) storing information representing a stall status of the execution units. Then, a step c) is performed, wherein, for each unexecuted sequence of the plurality of sequences: i) all of the plurality of execution units other than the subset which corresponds to the unexecuted sequence are stalled, and ii) the sequence of instructions is executed by the corresponding subset. Thereafter, it is determined in a step d) whether a current stall status of the plurality of execution units matches the stall status represented by the stored information. When there is no match, the steps b) through d) are repeated until there is a match in which the current stall status represented by the stored information matches the stored information.

摘要翻译： 提供了一种用于在具有由单个指令单元操作的多个执行单元的处理器上执行多个并行可执行指令序列的方法。 该方法包括：a）从提供给处理器的指令中检测适于并行执行的多个指令序列，其中每个序列适于由多个执行单元的子集执行，以及b）存储表示 执行单位。 然后，执行步骤c），其中对于多个序列中的每个未执行的序列：i）除了对应于未执行的序列的子集之外的所有多个执行单元都被停止，以及ii）指令序列 由相应的子集执行。 此后，在步骤d）中确定多个执行单元的当前失速状态是否与由所存储的信息表示的停顿状态相匹配。 当不匹配时，重复步骤b）至d），直到存在由所存储的信息表示的当前停顿状态与存储的信息匹配的匹配。

公开(公告)号：US20050144594A1

公开(公告)日：2005-06-30

申请号：US10858844

申请日：2004-06-02

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F13/00 ,  G06F9/45 ,  H04L12/24 ,  H04L12/28

CPC分类号： H04L41/0226 ,  H04L41/0873

摘要： A system of a network comprising a router, first switch, firewall, second switch, load sharing unit, third switch, and server firmware is managed in an operation management integration node as an internal component of a virtual node. The operation management integration node enables a person in charge of operation to set each device in a common command format, and after converting the common format into the command for each device, the operation management integration node inputs said command to each device to set each device. Also, the operation management integration node checks the consistency of the definitions set for the common format.

摘要翻译： 在作为虚拟节点的内部组件的操作管理集成节点中管理包括路由器，第一交换机，防火墙，第二交换机，负载共享单元，第​​三交换机和服务器固件的网络的系统。 操作管理集成节点使得负责操作的人能够以每个设备的共同命令格式设置每个设备，并且在将公共格式转换成每个设备的命令之后，操作管理集成节点向每个设备输入所述命令以设置每个设备 。 此外，操作管理集成节点检查为通用格式设置的定义的一致性。

公开(公告)号：US20050078117A1

公开(公告)日：2005-04-14

申请号：US10967363

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/14 ,  G06F15/16 ,  G06F15/80 ,  G06F21/24 ,  H04L29/06

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于执行图形处理的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器中的一个可以对第一组图形数据执行图形处理，以产生第二组图形数据，另一个第二处理器可以在第二组上执行图形处理，以生成第三组图形数据。