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公开(公告)号：US20190164977A1
公开(公告)日：2019-05-30
申请号：US16226648
申请日：2018-12-20
Inventor： Ger-Pin Lin , Kuan-Chun Lin , Chi-Mao Hsu , Shu-Yen Chan , Shih-Fang Tzou , Tsuo-Wen Lu , Tien-Chen Chan , Feng-Yi Chang , Shih-Kuei Yen , Fu-Che Lee
IPC: H01L27/108 , H01L21/28
Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
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公开(公告)号：US20190157097A1
公开(公告)日：2019-05-23
申请号：US16152366
申请日：2018-10-04
Inventor： Feng-Yi Chang , Fu-Che Lee
IPC: H01L21/3105 , H01L21/768 , H01L21/02
Abstract: A semiconductor process for improving loading effects in planarization is provided including steps of forming multiple first protruding patterns on a first region and a second region of a substrate, wherein the pattern density of the first protruding patterns in the first region is larger than the one in the second region, forming a first dielectric layer on the substrate and the first protruding patterns, wherein the first dielectric layer includes multiple second protruding patterns corresponding to the first protruding patterns below, forming a second dielectric layer on the first dielectric layer, performing a first planarization process to remove parts of the second dielectric layer, so that the top surface of the second protruding patterns are exposed, performing an etch process to remove the second protruding patterns of the first dielectric layer, removing the remaining second dielectric layer, and performing another planarization process to the first dielectric layer.
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公开(公告)号：US20190109138A1
公开(公告)日：2019-04-11
申请号：US16211239
申请日：2018-12-06
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , H01L21/768
CPC classification number: H01L27/10885 , H01L21/76802 , H01L21/7682 , H01L21/76877 , H01L21/76897 , H01L27/10814 , H01L27/10823 , H01L27/10888 , H01L27/10894 , H01L27/10897
Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
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公开(公告)号：US20190100430A1
公开(公告)日：2019-04-04
申请号：US15801308
申请日：2017-11-01
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
Abstract: A method of forming a semiconductor device includes following steps. First of all, plural first openings and plural second openings are sequentially formed on a material layer disposed on a substrate, with the second openings across the first openings to form plural overlapped regions. Then, plural patterns arranged in an array arrangement are formed, with each pattern overlapped each overlapped region, respectively. After that, transferring the first openings, the second openings and the patterns to the material layer, to from plural material patterns in an array arrangement. In another embodiment of the present invention, the first openings and the second openings may be replaced by plural first patterns and plural second patterns, while the patterns are replaced by plural openings.
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公开(公告)号：US20190081134A1
公开(公告)日：2019-03-14
申请号：US16114217
申请日：2018-08-28
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L49/02 , H01L27/08 , H01L27/108 , H01L21/3213
Abstract: The present invention relates to a method of forming a memory capacitor. A substrate is provided with a plurality of storage node contacts. A patterned supporting structure is formed on the substrate, following by forming a bottom electrode conformally on surface of plural openings in the patterned supporting structure, thereby contacting the storage node contacts. A sacrificial layer is formed in the opening. A soft etching process is performed to remove the bottom electrode on top and partial sidewall of the patterned supporting structure, wherein the soft etching process includes using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound. The sacrificial layer is completely removed away. A capacitor dielectric layer and a top electrode are formed on the bottom electrode layer.
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Patent Agency Ranking
公开(公告)号：US20190074279A1
公开(公告)日：2019-03-07
申请号：US16172845
申请日：2018-10-28
Inventor： Feng-Yi Chang , Fu-Che Lee
IPC: H01L27/108 , H01L23/535
CPC classification number: H01L27/10814 , H01L23/535 , H01L27/10855
Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.
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公开(公告)号：US20190043865A1
公开(公告)日：2019-02-07
申请号：US15947856
申请日：2018-04-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L27/108
Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.
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公开(公告)号：US20190035743A1
公开(公告)日：2019-01-31
申请号：US16003090
申请日：2018-06-07
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan , Chia-Liang Liao , Yu-Cheng Tung , Chien-Hao Chen , Chia-Hung Wang
IPC: H01L23/544 , H01L27/108
CPC classification number: H01L23/544 , H01L21/31116 , H01L21/31144 , H01L27/108 , H01L27/10808 , H01L27/10852 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
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公开(公告)号：US20190035631A1
公开(公告)日：2019-01-31
申请号：US16003058
申请日：2018-06-07
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L21/033 , H01L27/108
Abstract: A patterning method is disclosed. A substrate having a hard mask layer and a first material layer formed thereon is provided. The first material layer is patterned into first array patterns and first peripheral patterns. The first array patterns are further transferred into first spacer patterns. Subsequently, a planarization layer and a second material layer are successively formed on the substrate. The second material layer is patterned into second array patterns and second peripheral patterns. The second array patterns are further transferred into second spacer patterns. The second spacer patterns partially overlap the first spacer patterns. The second peripheral patterns do not overlap the first peripheral pattern. The first spacer patterns not overlapped by the second spacer patterns are removed to obtain third array patterns. The hard mask layer is then etched using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask.
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公开(公告)号：US10186513B2
公开(公告)日：2019-01-22
申请号：US15884415
申请日：2018-01-31
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , H01L21/768
Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
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