公开(公告)号：US20210217885A1

公开(公告)日：2021-07-15

申请号：US17197075

申请日：2021-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US11038066B2

公开(公告)日：2021-06-15

申请号：US16819148

申请日：2020-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/76 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66

Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

公开(公告)号：US11011486B1

公开(公告)日：2021-05-18

申请号：US16675200

申请日：2019-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.

公开(公告)号：US20210098623A1

公开(公告)日：2021-04-01

申请号：US17120243

申请日：2020-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/033 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A method of forming a semiconductor structure includes: providing a substrate including an upper surface, a gate structure disposed on the upper surface, a spacer disposed on a sidewall of the gate structure, a first region in the substrate, and a second region in the substrate; masking the second region and amorphizing the first region, such that an amorphous layer is formed in the first region; depositing a stress layer on the substrate, wherein the stress layer conformally covers the gate structure, the spacer, the first region and the second region; and recrystallizing the amorphous layer, thereby forming a dislocation in the first region.

公开(公告)号：US10903125B2

公开(公告)日：2021-01-26

申请号：US16261494

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device includes a substrate having a top surface, a source region in the substrate, a drain region in the substrate, a recessed trench extending from the top surface into the substrate and between the source region and the drain region, a stress-inducing material layer in the recessed trench, a channel layer on the stress-inducing material layer, and a gate structure on the channel layer. The recessed trench has a hexagonal cross-sectional profile.

公开(公告)号：US20200328298A1

公开(公告)日：2020-10-15

申请号：US16411053

申请日：2019-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/205 ,  H01L29/423

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20200227554A1

公开(公告)日：2020-07-16

申请号：US16260158

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L21/033

Abstract: A semiconductor device includes a substrate having an upper surface; a source region in the substrate; a drain region in the substrate and spaced apart from the source region; a channel region between the source region and the drain region; a gate structure on the channel region; m dislocations in the source region, wherein m is an integer greater than or equal to 1; and n dislocations in the drain region, wherein n is an integer greater than or equal to 0, and wherein m is greater than n.

公开(公告)号：US20170033198A1

公开(公告)日：2017-02-02

申请号：US14813127

申请日：2015-07-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/31

CPC classification number: H01L29/66795 ,  H01L21/02636 ,  H01L21/265 ,  H01L21/31 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848

Abstract: A fabricating method of a strained FET includes providing a semiconductive layer having a gate structure disposed thereon, wherein an epitaxial layer is embedded in the semiconductive layer aside the gate structure. Later, an element supply layer is formed to contact the epitaxial layer, wherein the element supply layer and the epitaxial layer have at least one identical element besides silicon. Finally, a thermal process is performed to drive the element into the epitaxial layer.

Abstract translation: 应变FET的制造方法包括提供其上设置有栅极结构的半导体层，其中除栅极结构之外的外延层嵌入在半导体层中。 然后，形成与外延层接触的元件供给层，其中除了硅之外，元件供给层和外延层具有至少一个相同的元素。 最后，进行热处理以将元件驱动到外延层中。

公开(公告)号：US09530841B1

公开(公告)日：2016-12-27

申请号：US14960442

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/32 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  B82Y10/00

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L21/26506 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7847 ,  H01L29/7848

Abstract: A gate-all-around (GAA) nanowire field-effect transistor (FET) device includes a semiconductor substrate, a nanowire on the semiconductor substrate, a gate structure surrounding a central portion of the nanowire, a source/drain region on either side of the gate structure, and at least one dislocation plane in the source/drain region.

Abstract translation: 栅极全能（GAA）纳米线场效应晶体管（FET）器件包括半导体衬底，半导体衬底上的纳米线，围绕纳米线的中心部分的栅极结构， 栅极结构和源/漏区中的至少一个位错平面。