公开(公告)号：US20090120193A1

公开(公告)日：2009-05-14

申请号：US12120073

申请日：2008-05-13

Applicant: Nicolas Abele

Inventor： Nicolas Abele

IPC: G01H11/06 ,  H01L21/56

CPC classification number: G01N9/002 ,  G01G3/165

Abstract: A micro scale includes one substrate forming a first zone constituting a first terminal, one conducting vibrating beam which has two opposite ends affixed on two supporting areas on the substrate, the conductive beam forming a second terminal; wherein the conductive beam is made of polymer gel having metallic microparticles in low quantity so as to avoid any contamination of a biological material to measure, the density of the metallic microparticles being high enough to achieve electrical conduction of the second terminal. A manufacturing process of such a micro scale circuit is also provided.

Abstract translation: 微尺度包括形成构成第一端子的第一区域的一个衬底，一个导电振动梁，其具有固定在衬底上的两个支撑区域上的两个相对端，所述导电梁形成第二端子; 其特征在于，所述导电性束由低分子量金属微粒的聚合物凝胶构成，以避免对所述生物材料的任何污染物进行测量，所述金属微粒的密度足够高以实现所述第二末端的导电。 还提供了这种微尺度电路的制造工艺。

公开(公告)号：US07525400B2

公开(公告)日：2009-04-28

申请号：US11427591

申请日：2006-06-29

Applicant: Jean-Francois Carpentier ,  Cyrille Tilhac

Inventor： Jean-Francois Carpentier ,  Cyrille Tilhac

IPC: H03H9/56

CPC classification number: H03H9/6433 ,  H03H9/58

Abstract: A band pass filtering circuit based on a quadripole includes a serial branch having a first acoustic resonator presenting a frequency of resonance and a frequency of anti-resonance and mounted in serial with a first capacitor; a parallel branch having a second acoustic resonator resulting from the same manufacturing process as the first resonator and mounted in parallel with a second capacitor of identical value to that the first capacitor. The filtering circuit is particularly but not exclusively adapted to the realization of integrated filtering circuits used in mobile telephony.

Abstract translation: 基于四极的带通滤波电路包括具有呈现谐振频率的第一声谐振器和反共振频率并与第一电容器串联安装的串行分支; 具有由与第一谐振器相同的制造工艺产生的第二声谐振器的并联支路，并且与第一电容器具有相同值的第二电容器并联安装。 滤波电路特别但不排他地适用于在移动电话中使用的集成滤波电路的实现。

公开(公告)号：US07512852B2

公开(公告)日：2009-03-31

申请号：US11041514

申请日：2005-01-24

Applicant: Frédéric Bancel ,  David Hely

Inventor： Frédéric Bancel ,  David Hely

IPC: G01R31/28

CPC classification number: G06F21/79 ,  G01R31/31719 ,  G01R31/318536

Abstract: An electronic circuit, including; a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connecting control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.

Abstract translation: 一种电子电路，包括 具有多个逻辑单元的逻辑电路; 存储单元能够形成移位寄存器，能够连接到逻辑单元; 具有用于接收识别密钥的输入的连接控制模块，所述模块连接所述存储单元，以便当所述接收输入接收到有效的识别密钥时形成测试移位寄存器，并且所述模块连接所述存储单元以形成 当输入没有接收到有效的识别密钥时，随机分配电路。 本发明允许电子电路在读取或写入模式下被防止欺诈性访问。 本发明还涉及包括该电子电路的智能卡。

公开(公告)号：US07495520B2

公开(公告)日：2009-02-24

申请号：US11835821

申请日：2007-08-08

Applicant: Pascal Mellot

Inventor： Pascal Mellot

IPC: H03C3/00 ,  H04L27/12

CPC classification number: H04L27/12 ,  G06F1/0321 ,  G06F1/0353

Abstract: A frequency-shift modulation device includes an oscillating circuit, a phase-locked loop and a digital frequency modulation circuit. The oscillating circuit is connected to the phase-locked loop in order to produce a fixed-frequency clock signal. This clock signal is used for timing the frequency modulation circuit. A standard model crystal oscillator can be used in the oscillating circuit, given that the RF frequency of a wireless transmission signal which is produced by the modulation device is determined digitally.

Abstract translation: 频移调制装置包括振荡电路，锁相环和数字频率调制电路。 振荡电路连接到锁相环，以产生固定频率时钟信号。 该时钟信号用于定时调频电路。 考虑到由调制装置产生的无线传输信号的RF频率是数字确定的，振荡电路中可以使用标准型晶体振荡器。

公开(公告)号：US07492639B2

公开(公告)日：2009-02-17

申请号：US11754707

申请日：2007-05-29

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  H01L27/115

Abstract: The present invention relates to a method for programming or erasing memory cells that include a selection transistor connected to a floating-gate transistor. According to the method, a non-zero compensation voltage is applied to the gate of a transistor not involved in the programming or erasing process so as to increase a breakdown threshold of the transistor, and an inhibition voltage is applied to the gate or to a terminal of at least one floating-gate transistor connected to the transistor having its breakdown threshold increased to inhibit a phenomenon of soft programming or soft erase of the floating-gate transistor.

Abstract translation: 本发明涉及一种编程或擦除存储单元的方法，该存储单元包括连接到浮栅晶体管的选择晶体管。 根据该方法，将非零补偿电压施加到不参与编程或擦除处理的晶体管的栅极，以增加晶体管的击穿阈值，并且将抑制电压施加到栅极或栅极 连接到具有其击穿阈值的晶体管的至少一个浮栅晶体管的端子增加以抑制浮动栅极晶体管的软编程或软擦除现象。

公开(公告)号：US07486582B2

公开(公告)日：2009-02-03

申请号：US11346796

申请日：2006-02-03

Applicant: François Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

Inventor： François Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract translation: 一种DRAM及其在具有控制电路的移动电话电路中的应用，该控制电路包括由第一时钟信号控制的第一更新控制器和由具有小于第一时钟信号频率的第二时钟信号控制的第二更新控制器，并且用于同步 GSM网络的事件。

公开(公告)号：US07476574B2

公开(公告)日：2009-01-13

申请号：US11335857

申请日：2006-01-19

Applicant: Michel Marty ,  Grégory Avenier

Inventor： Michel Marty ,  Grégory Avenier

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/76286

Abstract: An integrated circuit semiconductor substrate includes an active silicon layer separated from a silicon substrate layer by a buried insulating material layer. The active silicon layer, however, locally includes at least one over-thickness on the side of the buried layer, while maintaining a flat surface state of the semiconductor layer across the integrated circuit. The over-thickness is created by forming a cavity under the active silicon layer in the local area, and then providing the over-thickness by partially filling the cavity at the bottom of the active silicon layer through epitaxial growth. An insulating layer then fills the remaining portions of the cavity.

Abstract translation: 集成电路半导体衬底包括通过掩埋绝缘材料层与硅衬底层分离的活性硅层。 然而，活性硅层在掩埋层的侧面局部地包括至少一个厚度，同时保持跨越集成电路的半导体层的平坦表面状态。 通过在局部区域中的有源硅层下方形成空腔，然后通过外延生长部分填充有源硅层底部的空腔来提供厚度来产生厚度。 绝缘层然后填充空腔的剩余部分。

公开(公告)号：US07472834B2

公开(公告)日：2009-01-06

申请号：US10886934

申请日：2004-07-08

Applicant: Jérôme Conraux ,  Pierre Rizzo

Inventor： Jérôme Conraux ,  Pierre Rizzo

IPC: G06K19/06

CPC classification number: G06K19/07769 ,  G06K7/0008 ,  G06K19/0723

Abstract: A dual-mode smart card comprising several pads of physical contact with an external reader and two pads of connection to an antenna for a contactless operation, and comprising a voltage regulator capable of extracting from a radio frequency excitation reaching the antenna, a supply voltage of the chip's processing circuits, this regulator being controllable by a central circuit to be deactivated in the presence of a supply voltage on contacts of the chip.

Abstract translation: 一种双模智能卡，包括与外部读取器物理接触的多个焊盘和用于非接触操作的两个与天线的连接焊盘，并且包括能够从到达天线的射频激励提取的电压调节器， 芯片的处理电路，该调节器可由中央电路控制，以便在芯片的触点上存在电源电压时被去激活。

公开(公告)号：US20080280206A1

公开(公告)日：2008-11-13

申请号：US12118036

申请日：2008-05-09

Applicant: Sami Oukassi

Inventor： Sami Oukassi

IPC: H01M4/48 ,  H01M4/08

CPC classification number: H01M4/0426 ,  H01M2/10 ,  H01M4/139 ,  H01M4/485 ,  H01M4/5825 ,  H01M10/0436 ,  H01M10/0585 ,  H01M2004/028 ,  H01M2010/4292

Abstract: A process for realizing a positive electrode of a lithium-ion battery utilizes deposition by cathode sputtering in several steps. Two successive deposition steps are separated by a cooling of the electrode during its realization, a first intermediate step of sputtering the target without introducing oxygen, and a second intermediate step of sputtering the target while introducing oxygen. The electrode obtained is of amorphous vanadium oxide and exhibits good capacity and reversibility.

Abstract translation: 用于实现锂离子电池的正极的方法通过阴极溅射在几个步骤中进行沉积。 通过在其实现期间电极的冷却来分离两个连续的沉积步骤，在不引入氧的情况下溅射靶的第一中间步骤和在引入氧气的同时溅射靶的第二中间步骤。 得到的电极是无定形氧化钒，具有良好的容量和可逆性。

公开(公告)号：US20080259221A1

公开(公告)日：2008-10-23

申请号：US12106220

申请日：2008-04-18

Applicant: Jean-Claude Longchambon ,  Jean Nivet ,  Denis Dutoit

Inventor： Jean-Claude Longchambon ,  Jean Nivet ,  Denis Dutoit

IPC: H04N5/66 ,  G06F13/38 ,  G06F13/12

CPC classification number: H04N21/23602 ,  H04M1/72527 ,  H04N21/4122 ,  H04N21/4126 ,  H04N21/41407 ,  H04N21/4342 ,  H04N21/43632 ,  H04N21/4402 ,  H04N2201/0034 ,  H04N2201/0065 ,  H04N2201/0096

Abstract: Circuitry for providing an output video signal from a portable device to an external display, the circuitry including a processor block with an image processor, and a video encoder block with a video encoder for providing the output video signal to the external display, the processor block and the video encoder block being connected to each other by a serial interface arranged to provide image date from the processor block to the video encoder, the serial interface having at least one data lane and at least one first clock lane, wherein the video encoder block includes a first input connected to the at least one data lane for receiving image data and a second input connected to the at least one first clock lane for receiving a first clock signal, and wherein at least one of the video encoder block and the processor block has a third input arranged to receive a control signal for controlling data flow over the serial interface.

Abstract translation: 用于从便携式设备向外部显示器提供输出视频信号的电路，所述电路包括具有图像处理器的处理器块，以及具有用于将输出视频信号提供给外部显示器的视频编码器的视频编码器块，处理器块 并且所述视频编码器块通过布置成从所述处理器块提供图像日期到所述视频编码器的串行接口彼此连接，所述串行接口具有至少一个数据通道和至少一个第一时钟通道，其中所述视频编码器块 包括连接到所述至少一个用于接收图像数据的数据通道的第一输入和连接到所述至少一个第一时钟通道以用于接收第一时钟信号的第二输入，并且其中所述视频编码器块和所述处理器块中的至少一个 具有布置成接收用于控制串行接口上​​的数据流的控制信号的第三输入。