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公开(公告)号：US20170345385A9
公开(公告)日：2017-11-30
申请号：US14146061
申请日：2014-01-02
Applicant: SITRONIX TECHNOLOGY CORP.
Inventor： MIN-NAN LIAO
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3688 , G09G2310/027 , G09G2320/0276 , Y10T29/4913
Abstract: The present invention relates to an area-saving driving circuit for a display panel, which comprises a plurality of digital-to-analog converting circuits convert input data, respectively, and produce a pixel signal. A plurality of driving units are coupled to the plurality of digital-to-analog converting circuits, respectively. They produce a driving signal according to the pixel signal and transmit the driving signal to the display panel for displaying. A plurality of voltage booster units are coupled to the plurality of driving units, respectively, and produce a supply voltage according to a control signal. Then the supply voltage is provided to the plurality of driving units. Thereby, by providing the supply voltage to the plurality of driving units of the display panel by means of the plurality of voltage booster units, the area of the external storage capacitor is reduced. Alternative, the external storage capacitor can be even not required.
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公开(公告)号：US09779697B2
公开(公告)日：2017-10-03
申请号：US14810469
申请日：2015-07-27
Applicant: Sitronix Technology Corp.
Inventor： Chih-Hsiung Lin , Yung-Sheng Tseng
CPC classification number: G09G5/363 , G09G3/20 , G09G5/373 , G09G2330/00 , G09G2330/08 , G09G2330/10 , G09G2340/0414 , G09G2340/0421 , G09G2380/10
Abstract: A display apparatus for displaying a display information includes a display panel, and a plurality of gate drivers and a plurality of source drivers coupled to the display panel. When one abnormal driver exists among the plurality of gate drivers and the plurality of source drivers, the other functionally operating gate drivers and source drivers transform the display information into a transformed display information to transmit the transformed display information to the display panel for a display operation.
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公开(公告)号：US09773746B2
公开(公告)日：2017-09-26
申请号：US15190147
申请日：2016-06-22
Applicant: Sitronix Technology Corp.
Inventor： Kuo-Wei Tseng , Po-Chi Chen
IPC: H01L29/40 , H01L21/44 , H01L23/00 , H01L23/498
CPC classification number: H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17
Abstract: An electronic element for an electronic apparatus includes a substrate; a bump, disposed on the substrate for electrically connecting the electronic apparatus; and at least one under bump metal layer, disposed between the bump and the substrate for the bump to be attached to the substrate; wherein the UBM layer forms a breach structure.
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公开(公告)号：US09716429B2
公开(公告)日：2017-07-25
申请号：US14819399
申请日：2015-08-05
Applicant: Sitronix Technology Corp.
Inventor： Min-Nan Liao
CPC classification number: H02M3/07 , G09G2330/02 , H02M1/36 , H02M2001/0048 , Y02B70/1491
Abstract: A power supply system includes a charging pump module including a plurality of charging pump circuits, wherein each charging pump circuit includes a plurality of transistor switches and is coupled to a flying capacitor set in parallel and the flying capacitor set includes a plurality of flying capacitor units; and a control module for generating a plurality of control signals to switch a connection relationships of the plurality of flying capacitor units; wherein the plurality of charging pump circuits charges the plurality of flying capacitor units and the connection relationships of the plurality of flying capacitor units determines a generation of a charging voltage; an amplifying module for utilizing the charging voltage as a voltage source to generate an amplifying voltage; and a load module for processing a dynamic charging operation in a predetermined period according to the amplifying voltage, to make the load module achieve a predetermined voltage.
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公开(公告)号：US09614515B2
公开(公告)日：2017-04-04
申请号：US15060995
申请日：2016-03-04
Applicant: Artinfac Technology Corp. , Sitronix Technology Corp.
Inventor： Shih-Chiang Sun
IPC: H03K17/296 , H03K17/08 , H03K17/60 , H03K17/687 , H03K17/74 , H03K17/28
CPC classification number: H03K17/08 , H03K17/28 , H03K17/60 , H03K17/687 , H03K17/74 , H03K2217/0009
Abstract: The present invention disclosed an electrical dual control switch device and the method of controlling thereof. By applying two electrical switches with connection method of conventional mechanical type dual control switch device. The operating status of the electrical switch could be detected by the AC waveform of the power transmission line of the other electrical switch. Therefore, the objection of electrical controlling the loading device will be realized. The loading device could be remotely control and the usage of the power could also effectively calculate. Further the present invention could also protected against overload, work with touch device and sets a timer for automatically shut down the power.
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Patent Agency Ranking
136.发明授权公开(公告)号：US09602104B2
公开(公告)日：2017-03-21
申请号：US14642779
申请日：2015-03-10
Applicant: Sitronix Technology Corp.
Inventor： Ming-Wei Hsu , Chern-Lin Chen
CPC classification number: H03K19/0027 , G09G3/3688 , G09G2310/0291 , H03F3/3022 , H03F3/3023 , H03F3/45183 , H03F3/45192 , H03F3/45246 , H03F3/45475 , H03F3/45744 , H03F3/45968 , H03F2203/45212
Abstract: An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output buffer according to a data signal from a data input terminal of the output buffer; a reference voltage generator, for generating a reference voltage and inputting the reference voltage to the operational amplifier; and a sampling capacitor, coupled between a second input terminal of the operational amplifier and the data input terminal of the output buffer in a first phase, and coupled between the second input terminal of the operational amplifier and an output terminal of the operational amplifier in a second phase, wherein the second input terminal of the operational amplifier is further coupled to the output terminal of the operational amplifier in the first phase. The output signal outputs the data signal where the offset voltage is cancelled in the second phase.
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公开(公告)号：US09559696B2
公开(公告)日：2017-01-31
申请号：US15183776
申请日：2016-06-15
Applicant: Sitronix Technology Corp.
Inventor： Min-Nan Liao
IPC: H03K3/00 , H03K19/003 , H03K19/0185 , H03K17/687 , G09G3/36
CPC classification number: H03K19/00315 , G09G3/3677 , G09G2310/0289 , G09G2310/0291 , H03K17/687 , H03K19/018507
Abstract: A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a first transistor and a second transistor. The first transistor includes a first terminal and a second terminal electrically connected to an input terminal and an output terminal of the circuit buffer respectively, a third terminal electrically connected to a first power supply terminal, and a fourth terminal electrically connected to the third terminal of the first transistor. The second transistor includes a first terminal and a second terminal electrically connected to the input terminal and the output terminal of the circuit buffer respectively, a third terminal electrically connected to a second power supply terminal, and a fourth terminal electrically connected to the third terminal of the second transistor. Voltages of the first and second power supply terminal are switched between two different levels, respectively.
Abstract translation: 用于输出具有大于电路缓冲器中的任何电路元件的耐受电压的电压信号的电路缓冲器包括第一晶体管和第二晶体管。 第一晶体管包括分别电连接到电路缓冲器的输入端子和输出端子的第一端子和第二端子，电连接到第一电源端子的第三端子和电连接到第一端子的第三端子的第四端子 第一个晶体管。 第二晶体管包括分别电连接到电路缓冲器的输入端子和输出端子的第一端子和第二端子，电连接到第二电源端子的第三端子和电连接到第二端子的第三端子 第二晶体管。 第一和第二电源端子的电压分别在两个不同的电平之间切换。
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138.发明授权公开(公告)号：US09467159B1
公开(公告)日：2016-10-11
申请号：US14930673
申请日：2015-11-03
Applicant: Sitronix Technology Corp.
Inventor： Hung-Yen Tai
CPC classification number: H03M1/1057 , H03M1/468
Abstract: An analog-to-digital converting device includes a converting module, for sampling an analog input voltage according to a plurality of sampling signals to generate a comparing voltage and generating a comparing signal according to the comparing voltage, wherein the converting module comprises a plurality of capacitors and each of the plurality of capacitors couples between one of the plurality sampling signals and the comparing voltage; a control module, for adjusting the plurality of sampling signals according to the comparing signal, to generate a digital signal corresponding to the analog input voltage, wherein a plurality of bits of the digital signal are respectively corresponding to the capacitances of the plurality of capacitors; and a calibration module, for adjusting the capacitances of the plurality of capacitors according to the digital signal.
Abstract translation: 一种模拟 - 数字转换装置包括转换模块，用于根据多个采样信号对模拟输入电压进行采样以产生比较电压并根据比较电压产生比较信号，其中转换模块包括多个 电容器，并且所述多个电容器中的每一个耦合在所述多个采样信号中的一个和所述比较电压之间; 控制模块，用于根据所述比较信号调整所述多个采样信号，以产生对应于所述模拟输入电压的数字信号，其中所述数字信号的多个位分别对应于所述多个电容器的电容; 以及校准模块，用于根据数字信号调整多个电容器的电容。
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公开(公告)号：US09438235B2
公开(公告)日：2016-09-06
申请号：US14460346
申请日：2014-08-14
Applicant: Sitronix Technology Corp.
Inventor： Min-Nan Liao
IPC: H03K19/003 , H03K19/0185 , H03K17/687
CPC classification number: H03K19/00315 , G09G3/3677 , G09G2310/0289 , G09G2310/0291 , H03K17/687 , H03K19/018507
Abstract: A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a first transistor and a second transistor. The first transistor includes a first terminal and a second terminal electrically connected to an input terminal and an output terminal of the circuit buffer respectively, a third terminal electrically connected to a first power supply terminal, and a fourth terminal electrically connected to the third terminal of the first transistor. The second transistor includes a first terminal and a second terminal electrically connected to the input terminal and the output terminal of the circuit buffer respectively, a third terminal electrically connected to a second power supply terminal, and a fourth terminal electrically connected to the third terminal of the second transistor. Voltages of the first and second power supply terminal are switched between two different levels, respectively.
Abstract translation: 用于输出具有大于电路缓冲器中的任何电路元件的耐受电压的电压信号的电路缓冲器包括第一晶体管和第二晶体管。 第一晶体管包括分别电连接到电路缓冲器的输入端子和输出端子的第一端子和第二端子，电连接到第一电源端子的第三端子和电连接到第一端子的第三端子的第四端子 第一个晶体管。 第二晶体管包括分别电连接到电路缓冲器的输入端子和输出端子的第一端子和第二端子，电连接到第二电源端子的第三端子和电连接到第二端子的第三端子 第二晶体管。 第一和第二电源端子的电压分别在两个不同的电平之间切换。
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公开(公告)号：US09202428B2
公开(公告)日：2015-12-01
申请号：US14135597
申请日：2013-12-20
Applicant: Sitronix Technology Corp.
Inventor： Chung-Hsin Su , Tsun-Sen Lin
IPC: G09G3/36 , G11C11/406 , G09G5/18 , G09G5/397
CPC classification number: G09G3/2092 , G09G3/3674 , G09G5/18 , G09G5/397 , G09G2320/0252 , G09G2330/021 , G11C11/406
Abstract: A method of refreshing a memory array for a driving circuit includes generating a word-line scanning signal corresponding to a word-line of a memory array, and turning on a plurality of memory cells corresponding to the word-line of the memory array according to the word-line scanning signal to refresh the plurality of memory cells corresponding to the word-line of the memory array, wherein the memory has a first number of bit-lines and a second number of word-lines.
Abstract translation: 刷新用于驱动电路的存储器阵列的方法包括：生成与存储器阵列的字线相对应的字线扫描信号，并根据存储器阵列的字线对应于多个存储单元 所述字线扫描信号刷新对应于所述存储器阵列的字线的多个存储单元，其中所述存储器具有第一数量的位线和第二数量的字线。
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