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1440 条记录 (耗时 0.032 秒)

    High output swing high voltage tolerant bus driver
    131.
    发明授权
    High output swing high voltage tolerant bus driver 有权

    公开(公告)号：US10461964B1

    公开(公告)日：2019-10-29

    申请号：US16169757

    申请日：2018-10-24

    申请人： Silicon Laboratories Inc.

    发明人： Alexander Cherkassky ,  Bruce P. Del Signore

    IPC分类号： H04L25/02

    摘要： A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

    NEUTRALIZATION OF PHASE PERTURBATIONS FROM DETERMINISTIC ELECTROMAGNETIC INTERFERENCE
    134.
    发明申请
    NEUTRALIZATION OF PHASE PERTURBATIONS FROM DETERMINISTIC ELECTROMAGNETIC INTERFERENCE 审中-公开

    公开(公告)号：US20190305783A1

    公开(公告)日：2019-10-03

    申请号：US15944567

    申请日：2018-04-03

    申请人： Silicon Laboratories Inc.

    发明人： Aaron J. Caffee ,  Russell Croman ,  Brian G. Drost

    IPC分类号： H03L7/093 ,  H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H05K1/02

    摘要： A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.

    Apparatus for Digital Phase-Locked Loop and Associated Methods
    137.
    发明申请
    Apparatus for Digital Phase-Locked Loop and Associated Methods 审中-公开

    公开(公告)号：US20190268008A1

    公开(公告)日：2019-08-29

    申请号：US15904173

    申请日：2018-02-23

    申请人： Silicon Laboratories Inc.

    发明人： John M. Khoury ,  Peijun Wang

    IPC分类号： H03L7/099 ,  H03L7/24 ,  G01K7/02

    摘要： An apparatus includes a digital phase-locked loop (DPLL). The DPLL includes a digital phase and frequency detector coupled to receive a reference signal and to generate a first set of output signals, and a digital loop filter that receives the first set of output signals of the phase and frequency detector output and generates an integral path control signal and a proportional path control signal. The DPLL further includes a digital to analog converter (DAC) to convert the integral path control signal and the proportional path control signal to a second set of output signals. The DPLL in addition includes a controlled oscillator (CO) to generate an output signal in response to the second set of output signals.

    ECC memory controller to detect dangling pointers
    138.
    发明授权
    ECC memory controller to detect dangling pointers 有权

    公开(公告)号：US10360104B2

    公开(公告)日：2019-07-23

    申请号：US15589217

    申请日：2017-05-08

    申请人： Silicon Laboratories Inc.

    发明人： Thomas S. David

    IPC分类号： G06F11/10 ,  G06F11/08 ,  G06F12/14

    摘要： A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

    State retention circuit that retains data storage element state during power reduction mode
    139.
    发明授权
    State retention circuit that retains data storage element state during power reduction mode 有权

    公开(公告)号：US10340894B1

    公开(公告)日：2019-07-02

    申请号：US15963316

    申请日：2018-04-26

    申请人： SILICON LABORATORIES INC.

    发明人： Thomas S. David ,  Wasim Quddus

    IPC分类号： H03K3/012 ,  H03K3/3562 ,  H03K17/24 ,  H03K3/289

    摘要： A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.