First-in, first-out (FIFO) memory cell architecture
    131.
    发明申请
    First-in, first-out (FIFO) memory cell architecture 审中-公开
    先进先出(FIFO)存储单元架构

    公开(公告)号:US20020048201A1

    公开(公告)日:2002-04-25

    申请号:US09948146

    申请日:2001-09-06

    Inventor: Anurag Garg

    CPC classification number: G11C11/412 G11C8/16

    Abstract: A first-in, first-out (FIFO) memory cell architecture is provided in which one node of the latch in the FIFO memory cell is connected to the gate of the pass transistor. Further, the bit line is connected to the source of the pass transistor, and the word line is connected to the drain of the pass transistor to provide a stable memory cell requiring less area for implementation.

    Abstract translation: 提供先入先出(FIFO)存储单元结构,其中FIFO存储单元中的锁存器的一个节点连接到传输晶体管的栅极。 此外,位线连接到传输晶体管的源极,并且字线连接到传输晶体管的漏极,以提供一个稳定的存储单元,其需要较少的实现面积。

    Programmable glitch filter
    132.
    发明申请
    Programmable glitch filter 有权
    可编程毛刺滤波器

    公开(公告)号:US20010048341A1

    公开(公告)日:2001-12-06

    申请号:US09864946

    申请日:2001-05-24

    CPC classification number: H03K5/1252

    Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

    Abstract translation: 毛刺滤波器包括用于存储作为滤波器的输出的当前状态的存储元件。 存储元件的输出连接到状态比较器的一个输入。 状态比较器的另一输入端连接到输入信号。 在状态比较器和存储元件之间连接可编程时钟延迟。 可编程时钟延迟可以提供独立于用于实现的技术的编程时间。 毛刺滤波器被布置成使得仅当输入信号改变然后在编程的持续时间内保持不变时,才将输入信号作为新的当前状态存储在存储元件中。

    ELECTRONIC CIRCUIT WITH THYRISTOR
    133.
    发明申请

    公开(公告)号:US20250132690A1

    公开(公告)日:2025-04-24

    申请号:US18962653

    申请日:2024-11-27

    Inventor: Laurent GONTHIER

    Abstract: The present description concerns a converter comprising an AC-DC conversion stage comprising a first thyristor, a first power supply circuit delivering a first reference voltage between a first node and a second node, and a second power supply circuit delivering a second reference voltage between third and fourth nodes, the cathode of the first thyristor being coupled to the first node of the first power supply circuit by a first switch and being connected to the fourth node, the second power supply circuit comprising a first rectifying element coupled to the second node of the first power supply circuit and coupled to the third node.

    Electronic circuit with thyristor
    134.
    发明授权

    公开(公告)号:US12184195B2

    公开(公告)日:2024-12-31

    申请号:US17736668

    申请日:2022-05-04

    Inventor: Laurent Gonthier

    Abstract: The present description concerns a converter comprising an AC-DC conversion stage comprising a first thyristor, a first power supply circuit delivering a first reference voltage between a first node and a second node, and a second power supply circuit delivering a second reference voltage between third and fourth nodes, the cathode of the first thyristor being coupled to the first node of the first power supply circuit by a first switch and being connected to the fourth node, the second power supply circuit comprising a first rectifying element coupled to the second node of the first power supply circuit and coupled to the third node.

    VOLTAGE CONVERTER
    135.
    发明公开
    VOLTAGE CONVERTER 审中-公开

    公开(公告)号:US20230412084A1

    公开(公告)日:2023-12-21

    申请号:US18209744

    申请日:2023-06-14

    Inventor: Laurent GONTHIER

    CPC classification number: H02M3/33571 H02M3/315

    Abstract: The present description concerns a circuit for converting from a first alternating voltage to a second voltage. The circuit includes: a first thyristor; a first control circuit of the first thyristor; a power factor correction circuit comprising a coil; and a first circuit configured to convert a third voltage into a fourth DC voltage. The third voltage corresponds to a difference between a potential at a first node connected to an output node of the coil and a reference potential. The fourth DC voltage is configured to supply the first control circuit of the first thyristor, and is referenced with respect to the same reference potential as the third voltage.

    System and method for display synchronization

    公开(公告)号:US11775117B1

    公开(公告)日:2023-10-03

    申请号:US17859784

    申请日:2022-07-07

    Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

    MICRO LENS ARRAYS AND METHODS OF FORMATION THEREOF

    公开(公告)号:US20220352232A1

    公开(公告)日:2022-11-03

    申请号:US17243195

    申请日:2021-04-28

    Inventor: Yu-Tsung Lin

    Abstract: A method of forming a device, the method including: depositing a first photoresist layer over a substrate, forming an array of seed lenses by patterning and reflowing the first photoresist layer, a dimension of the array of seed lenses varying across the substrate, forming a second photoresist layer over the array of seed lenses, and forming a microlens array by patterning and reflowing the second photoresist layer.

    MEMS RESONANCE CONTROL USING PHASE DETECTION

    公开(公告)号:US20220006988A1

    公开(公告)日:2022-01-06

    申请号:US17479176

    申请日:2021-09-20

    Abstract: A light projection system includes a MEMS mirror operating on a mirror drive signal to generate a mirror sense signal resulting from operation of the MEMS mirror based on the mirror drive signal. A mirror driver generates the mirror drive signal from a drive control signal. A controller receives the mirror sense signal from the MEMS mirror, obtains a first sample of the mirror sense signal at a first phase thereof, obtains a second sample of the mirror sense signal at a second phase thereof, wherein the first and second phases are separated by a half period of the mirror drive signal, with the second phase occurring after the first phase, and generates the drive control signal based on a difference between the first and second samples to keep the mirror drive signal separated in phase from the mirror sense signal by a desired amount of phase separation.

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