公开(公告)号：US20220208819A1

公开(公告)日：2022-06-30

申请号：US17556604

申请日：2021-12-20

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS PTE LTD

Inventor： David GANI ,  Yiying KUO

IPC: H01L27/146 ,  H01L23/498

Abstract: The present disclosure is directed to a package that includes a transparent layer that is on and covers a sensor of a die as well as a plurality of electrical connections that extend from a first surface of the package to the second surface of the package opposite to the first surface. In at least one embodiment of a package, the electrical connections each include a conductive structure that extends through the transparent layer to a first side of a corresponding contact pad of the die, and at least one electrical that extends into the second surface of the die to a second side of the corresponding contact pad that is opposite to the first side. In at least another embodiment of a package, the electrical connections include a conductive structure that extends through a molding compound to a first side of a corresponding contact pad of the die, and at least one electrical via that extends into the second surface of the die to a second side of the corresponding contact pad opposite to the first side.

公开(公告)号：US20210305438A1

公开(公告)日：2021-09-30

申请号：US17187510

申请日：2021-02-26

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS PTE LTD

Inventor： David GANI ,  Yiying KUO

IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0392

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP), with a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion having and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to a contact of the die within the package that extends from the transparent substrate to an active surface of the package. The active surface is utilized to mount the package within an electronic device or to a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer, and a second insulating layer on the conductive layer.

公开(公告)号：US20230307302A1

公开(公告)日：2023-09-28

申请号：US18184436

申请日：2023-03-15

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS PTE LTD

Inventor： David GANI ,  Hui-Tzu Wang

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/04 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/16151 ,  H01L2924/16788 ,  H01L2224/32225

Abstract: A semiconductor package includes a silicon substrate with an active surface and an inactive surface. A semiconductor device, such as an image, light, or optical sensor, is formed in the active surface and disposed on the substrate. A glass plate is coupled to the substrate with adhesive. The glass plate includes a sensor area that corresponds to the area of the semiconductor device and holes through the glass plate that are generally positioned around the sensor area of the glass plate. During formation of the package, the holes through the glass plate allow gas released by the adhesive to escape the package and prevent formation of a gas bubble.

公开(公告)号：US20220122941A1

公开(公告)日：2022-04-21

申请号：US17483076

申请日：2021-09-23

Applicant: STMicroelectronics PTE LTD

Inventor： Chun Yi TENG ,  David GANI

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78

Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

公开(公告)号：US20210327863A1

公开(公告)日：2021-10-21

申请号：US17360925

申请日：2021-06-28

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David GANI

IPC: H01L25/16 ,  G01S17/04 ,  H01S5/02325 ,  H01L21/768 ,  H01L23/48 ,  H01L31/02 ,  H01L31/167 ,  H01L31/18 ,  H04M1/02

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

公开(公告)号：US20200241068A1

公开(公告)日：2020-07-30

申请号：US16746201

申请日：2020-01-17

Applicant: STMicroelectronics Pte Ltd

Inventor： Pedro Jr Santos PERALTA ,  David GANI

IPC: G01R31/28 ,  G01R31/26 ,  G01R31/3185 ,  H01L21/66

Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

公开(公告)号：US20190195685A1

公开(公告)日：2019-06-27

申请号：US16213197

申请日：2018-12-07

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Laurent HERARD ,  David GANI

IPC: G01J1/02 ,  G01J1/42

CPC classification number: G01J1/0271 ,  G01J1/4204

Abstract: One or more embodiments are directed to ambient light sensor packages, and methods of making ambient light sensor packages. One embodiment is directed to an ambient light sensor package that includes an ambient light sensor die having opposing first and second surfaces, a light sensor on the first surface of the ambient light sensor die, one or more conductive bumps on the second surface of the ambient light sensor die, and a light shielding layer on at least the first surface and the second surface of the ambient light sensor die. The light shielding layer defines an opening over the light sensor. The ambient light sensor package may further include a transparent cover between the first surface of the ambient light sensor die and the light shielding layer, and an adhesive that secures the transparent cover to the ambient light sensor die.

公开(公告)号：US20240194709A1

公开(公告)日：2024-06-13

申请号：US18582860

申请日：2024-02-21

Applicant: STMicroelectronics PTE LTD

Inventor： Laurent HERARD ,  David GANI

IPC: H01L27/146

CPC classification number: H01L27/14618

Abstract: Disclosed herein is a method of reducing noise captured by an image sensor. The method includes affixing a bottom surface of a glass covering to the image sensor, permitting light to impinge upon the glass covering, and shaping the glass covering such that when the light that impinges upon the glass covering impinges upon a sidewall of the glass covering, the sidewall reflects the light on a trajectory away from the image sensor.

公开(公告)号：US20230197688A1

公开(公告)日：2023-06-22

申请号：US18166931

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L21/565 ,  H01L21/563 ,  H01L23/49866 ,  H01L25/16 ,  H01L23/13 ,  H01L24/32 ,  H01L23/49816 ,  H01L2224/05009 ,  H01L2225/06503 ,  H01L2224/32225

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US20220291277A1

公开(公告)日：2022-09-15

申请号：US17826705

申请日：2022-05-27

Applicant: STMicroelectronics Pte Ltd

Inventor： Pedro Jr Santos PERALTA ,  David GANI

IPC: G01R31/28 ,  H01L21/66 ,  G01R31/3185 ,  G01R31/26

Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.