公开(公告)号：US20190392188A1

公开(公告)日：2019-12-26

申请号：US16378201

申请日：2019-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Qiang WANG ,  Libin LIU

IPC: G06K9/00 ,  G06F3/043 ,  G01S7/52

Abstract: The present disclosure provides a signal receiving circuit and a driving method thereof, a display panel, and a display apparatus. The signal receiving circuit includes a reset circuit having an input terminal connected to a reference signal line for providing a reference voltage signal, a control terminal connected to a reset signal line providing a reset signal, and an output terminal connected to a collection node, the reset circuit being configured to control a voltage of a signal at the collection node under control of the reset signal; and an output circuit having an input terminal connected to the collection node, configured to accumulatively amplify the signal at the collection node and output the amplified signal.

公开(公告)号：US20190067387A1

公开(公告)日：2019-02-28

申请号：US16111411

申请日：2018-08-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Yipeng CHEN ,  Libin LIU

IPC: H01L27/32 ,  H01L51/56 ,  G09G3/3225 ,  H01L51/00

Abstract: Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a display area; an edge area; a bent portion between the display area and the edge area, the edge area being bent at a predetermined angle towards a side facing away from a display surface of the display area by means of the bent portion; and a row driving circuit in the edge area.

公开(公告)号：US20170193901A1

公开(公告)日：2017-07-06

申请号：US15233443

申请日：2016-08-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Qiang WANG ,  Libin LIU

IPC: G09G3/3241 ,  G09G3/3266 ,  H01L27/32 ,  G09G3/3291

CPC classification number: H01L27/3276 ,  G09G3/3233 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0245 ,  G09G2310/08 ,  G09G2320/043 ,  G09G2330/12 ,  H01L27/124 ,  H01L27/1255

Abstract: The present disclosure relates to a pixel circuit, a display substrate, a display device, and a method for driving the display substrate. The pixel circuit includes an offset control unit, which is connected between a reset control terminal and a first end of an electroluminescent unit and is configured to be turned on in a case that a reset control signal is applied to the reset control terminal, and to set a voltage of the first end of the electroluminescent unit to be a voltage of the reset control signal.

公开(公告)号：US20250166568A1

公开(公告)日：2025-05-22

申请号：US19032469

申请日：2025-01-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang SHANG ,  Jiangnan LU ,  Li WANG ,  Mengyang WEN ,  Xing YAO ,  Libin LIU

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275

Abstract: Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.

公开(公告)号：US20240324369A1

公开(公告)日：2024-09-26

申请号：US18734140

申请日：2024-06-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yipeng CHEN ,  Libin LIU ,  Yunfei LI

IPC: H10K59/131 ,  G09G3/3258 ,  H01L27/12 ,  H10K59/121

CPC classification number: H10K59/131 ,  G09G3/3258 ,  H10K59/1213 ,  H10K59/1216 ,  G09G2300/0842 ,  G09G2310/0262 ,  G09G2320/0209 ,  H01L27/124 ,  H01L27/1255

Abstract: Provided are a wiring structure of a pixel driving circuit, a display panel, and a display device. The wire layout includes: a first switching element, a second switching element and a driving transistor. A source electrode of the driving transistor is connected to a power signal line. The power signal line includes a first power signal line that is in a same direction as a data signal line, and the data signal line is arranged at a position of the first power signal line away from a gate electrode of the driving transistor.

公开(公告)号：US20240212598A1

公开(公告)日：2024-06-27

申请号：US17788727

申请日：2021-07-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiyu ZHAO ,  Libin LIU ,  Yu FENG ,  Li WANG ,  Yao HUANG ,  Benlian WANG ,  Weiyun HUANG ,  Rui WANG

IPC: G09G3/3233 ,  H10K59/121 ,  H10K59/126

CPC classification number: G09G3/3233 ,  G09G2300/0452 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/045 ,  G09G2330/021 ,  H10K59/1213 ,  H10K59/1216 ,  H10K59/126

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first initialization circuit and a reset circuit; the first initialization circuit configured to write a first initial voltage into the first end of the driving circuit under the control of an initialization control signal; the reset circuit is configured to write a reset voltage into the second end of the driving circuit or the first end of the driving circuit under the control of a second scan signal; the driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of a control end of the driving circuit.

公开(公告)号：US20240206266A1

公开(公告)日：2024-06-20

申请号：US18590203

申请日：2024-02-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan LU ,  Guangliang SHANG ,  Can ZHENG ,  Yu FENG ,  Libin LIU ,  Jie ZHANG ,  Mei LI

IPC: H10K59/131 ,  H10K59/80

CPC classification number: H10K59/131 ,  H10K59/8051

Abstract: Provided is an organic light-emitting diode display substrate, including: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein the source/drain layer includes at least one pair of first signal lines; the anode layer includes a common power line, wherein the common power line is provided with vent holes; overlapping areas between two first signal lines in each pair of the first signal lines and a projection pattern of the vent hole are equal, the overlapping area being greater than 0, wherein the projection pattern of the vent hole is a pattern of an orthographic projection of the vent hole in the common power line on the source/drain layer. A display panel and a display device are also provided.

公开(公告)号：US20240177662A1

公开(公告)日：2024-05-30

申请号：US17789918

申请日：2021-06-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Libin LIU ,  Jiangnan LU ,  Shimming SHI ,  Li WANG

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/066

Abstract: An array substrate and a display device are provided. The array substrate includes a plurality of pixel driving circuits, each of which includes a driving transistor, a first light emitting control transistor, a compensation transistor, a first initialization transistor and a second initialization transistor; a first electrode of the first initialization transistor and a first electrode of the first light emitting control transistor are connected to a first node; a first electrode of the second initialization transistor and a first electrode of the compensation transistor are connected to a second node, a second electrode of the first initialization transistor is configured to receive the first initialization signal, and a cathode of the light emitting element is configured to receive a first driving signal, and a difference between a potential of the first initialization signal and a potential of the first driving signal is less than 1.5V.

公开(公告)号：US20240169904A1

公开(公告)日：2024-05-23

申请号：US17788725

申请日：2021-07-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Libin LIU ,  Shiming SHI ,  Xiyu ZHAO ,  Yu FENG ,  Li WANG

IPC: G09G3/3225 ,  H10K59/121

CPC classification number: G09G3/3225 ,  H10K59/1213 ,  G09G2300/0452 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/045 ,  G09G2330/021

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first control circuit, a compensation control circuit and a first initialization circuit; the first control circuit is configured to control to connect the control end of the driving circuit and the connection node under the control of a first scan signal; the compensation control circuit is configured to control to connect the connection node and the first end of the driving circuit under the control of a second scan signal; the first initialization circuit is configured to write a first initialization voltage into the connection node under the control of an initialization control signal; the driving circuit is configured to control to connect the first end and a second end of the driving circuit under the control of a potential of the control end thereof.

公开(公告)号：US20240071312A1

公开(公告)日：2024-02-29

申请号：US17765045

申请日：2021-03-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang SHANG ,  Jiangnan LU ,  Long HAN ,  Li WANG ,  Libin LIU ,  Xinshe YIN ,  Shiming SHI

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/0286 ,  G11C19/287

Abstract: A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.