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149 条记录 (耗时 0.03 秒)

    Motion vector estimation apparatus
    131.
    发明申请
    Motion vector estimation apparatus 失效
    运动矢量估计装置

    公开(公告)号：US20070110161A1

    公开(公告)日：2007-05-17

    申请号：US11591451

    申请日：2006-11-02

    申请人： Katsuo Saigo ,  Tatsuro Juri ,  Hideyuki Ohgose ,  Koji Arimura ,  Hiroshi Arakawa ,  Kei Tasaka ,  Yuuki Maruyama

    发明人： Katsuo Saigo ,  Tatsuro Juri ,  Hideyuki Ohgose ,  Koji Arimura ,  Hiroshi Arakawa ,  Kei Tasaka ,  Yuuki Maruyama

    IPC分类号： H04N11/02 ,  H04N11/04

    CPC分类号： H04N19/57 ,  H04N19/513 ,  H04N19/56 ,  H04N19/61

    摘要： The present invention provides a motion vector estimation apparatus which can decrease circuit size by reducing the amount of computations for detecting a motion vector. The motion vector estimation apparatus in the present invention includes a motion vector estimation unit which estimates a motion vector MV0F for the target block BL0 by searching within a reference picture P1 for a block with an image similar to an image in the target block BL0, which is included in a picture B2; a prediction calculation unit and a prediction range control unit which specify a search range in the reference picture P1 based on the motion vector MV0F and; the motion vector estimation unit estimates the motion vector MV1F for the target block BL1 by searching in the search range for a block with an image similar to an image in the target block BL1, which is included in the picture B3.

    摘要翻译： 本发明提供一种通过减少用于检测运动矢量的计算量来减小电路尺寸的运动矢量估计装置。 本发明的运动矢量估计装置包括运动矢量估计单元，其通过在参考图像P 1中搜索具有与目标中的图像相似的图像的块来估计目标块BL 0的运动矢量MV 0 F 块BL 0，其包括在图片B 2中; 预测计算单元和预测范围控制单元，其基于运动矢量MV 0 F指定参考图像P 1中的搜索范围; 运动矢量估计单元通过在搜索范围内搜索具有与包括在图像B 3中的目标块BL 1中的图像类似的图像的块来估计目标块BL 1的运动矢量MV 1 F。

    Data processing method, data processing apparatus, and program recording medium
    132.
    发明授权
    Data processing method, data processing apparatus, and program recording medium 失效
    数据处理方法，数据处理装置和程序记录介质

    公开(公告)号：US07209634B2

    公开(公告)日：2007-04-24

    申请号：US10871281

    申请日：2004-06-21

    申请人： Tadashi Ono ,  Tatsuro Juri

    发明人： Tadashi Ono ,  Tatsuro Juri

    IPC分类号： H04N7/00 ,  H04N7/26

    CPC分类号： H04N5/781 ,  G06T1/0007 ,  H04N7/01 ,  H04N7/0135

    摘要： When inputting moving image data into a personal computer for display or for recording on a recording medium, there often occur cases where processing cannot catch up with the input, resulting in interruption of the processing. Also, when performing conversion from an input digital signal having an arbitrary number of samples to an output digital signal having an arbitrary number of samples, prior art methods entail the possibility that the memory capacity and the amount of computation may become enormous. In view of this, according to the present invention, if the image processing cannot catch up with the input, the data is re-input for processing by utilizing information concerning the recorded position, the recorded time, or the time at which playback is to be performed; this achieves the same effect as processing continuous moving image data without interruption.

    摘要翻译： 当将运动图像数据输入到用于显示或记录在记录介质上的个人计算机时，经常发生处理不能赶上输入的情况，导致处理中断。 此外，当从具有任意数量的样本的输入数字信号执行到具有任意数量样本的输出数字信号的转换时，现有技术的方法需要存储器容量和计算量可能变得巨大的可能性。 鉴于此，根据本发明，如果图像处理不能赶上输入，则通过利用关于记录位置，记录时间或播放时间的信息重新输入数据以进行处理 被执行 这实现了与中断处理连续运动图像数据相同的效果。

    Data recording apparatus, medium and information package
    133.
    发明授权
    Data recording apparatus, medium and information package 有权
    数据记录设备，介质和信息包

    公开(公告)号：US07162144B1

    公开(公告)日：2007-01-09

    申请号：US09692312

    申请日：2000-10-20

    申请人： Tadashi Ono ,  Tatsuro Juri

    发明人： Tadashi Ono ,  Tatsuro Juri

    IPC分类号： H04N5/93 ,  H04N5/91

    CPC分类号： G11B20/00768 ,  G11B20/00 ,  G11B20/00086 ,  G11B20/10

    摘要： A data recording apparatus that sequentially input: data configured in units that cannot be recorded across different files and records the data in a file having a predetermined volume, has: size detecting unit for deciding when data is sequentially recorded in file, whether next unit of the data to be recorded can be fully recorded in the same file, or not; file creation controlling unit for recording said next data to be recorded in another file or stopping recording if the case where the result of the decision by said size detecting unit shows that recording is not possible; and file writing unit for writing data in a file according to the control from said file creation controlling unit.

    摘要翻译： 一种数据记录装置，其顺序地输入：以不能被记录在不同文件之外的单元配置的数据并将数据记录在具有预定音量的文件中的数据记录装置具有：尺寸检测单元，用于决定何时数据被顺序记录在文件中， 要记录的数据可以完全记录在同一个文件中; 文件创建控制单元，用于如果所述尺寸检测单元的判定结果显示不能进行记录的情况，则记录要记录在另一文件中的下一个数据或停止记录; 以及文件写入单元，用于根据来自所述文件创建控制单元的控制在文件中写入数据。

    Coding method and apparatus for input image data and a recording medium performing such method
    134.
    发明授权
    Coding method and apparatus for input image data and a recording medium performing such method 失效
    用于输入图像数据的编码方法和装置以及执行这种方法的记录介质

    公开(公告)号：US07050644B2

    公开(公告)日：2006-05-23

    申请号：US10786147

    申请日：2004-02-26

    申请人： Tatsuro Juri ,  Tadashi Ono

    发明人： Tatsuro Juri ,  Tadashi Ono

    IPC分类号： G06K9/46 ,  G06K9/34

    CPC分类号： H04N19/88 ,  H04N19/124 ,  H04N19/126 ,  H04N19/13 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/30 ,  H04N19/423 ,  H04N19/60 ,  H04N19/61 ,  H04N19/90 ,  H04N19/91

    摘要： The present invention includes methods and apparatus for attaining high speed coding and decoding. A first method decreases the number of memory access times by performing signal format conversion, orthogonal transform and continuous variable-length coding with predetermined small areas in a frame used as units. A second method omits orthogonal transform computation by using orthogonal transform coefficients to shorten the processing time. A third method uses additions and subtractions for orthogonal transform thereby decreasing the number of registers used and reducing the number of memory access times. The present invention further includes a decoding method for variable-length decoding wherein table size is not made larger because the number of table access times per code word is set to a maximum of 2, and plural code words are decoded by one table access operation to attain high-speed decoding.

    摘要翻译： 本发明包括用于实现高速编码和解码的方法和装置。 第一种方法是通过执行信号格式转换，正交变换和连续可变长度编码来减少存储器访问次数，并且使用作为单位的帧中的预定小区域进行连续可变长度编码。 第二种方法通过使用正交变换系数来省略正交变换计算，以缩短处理时间。 第三种方法使用加法和减法进行正交变换，从而减少使用的寄存器数量并减少存储器访问次数。 本发明还包括一种用于可变长度解码的解码方法，其中，由于每个码字的表访问次数被设置为最大值2，所以表大小不大，并且通过一个表访问操作将多个码字解码为 达到高速解码。

    Image signal processing device and method
    135.
    发明申请
    Image signal processing device and method 失效
    图像信号处理装置及方法

    公开(公告)号：US20060087565A1

    公开(公告)日：2006-04-27

    申请号：US11252834

    申请日：2005-10-18

    申请人： Kazuo Okamoto ,  Tatsuro Juri ,  Yuji Nagaishi ,  Takuma Chiba

    发明人： Kazuo Okamoto ,  Tatsuro Juri ,  Yuji Nagaishi ,  Takuma Chiba

    IPC分类号： H04N5/228

    CPC分类号： H04N5/23248 ,  H04N5/144 ,  H04N5/2353 ,  H04N5/3454 ,  H04N5/3532

    摘要： When a method or apparatus of assuring simultaneous exposure, such as a mechanical shutter, is not provided with a MOS imaging sensor, moving subjects are distorted with a MOS image sensor when capturing a still image of a fast-moving subject because imaging and reading are not simultaneous across the MOS sensor. Changing the MOS sensor exposure sequence and reading sequence, and interpolating the read data, change and correct the read sequence line by line when imaging a high resolution moving image, and thus improve distortion in moving subjects.

    摘要翻译： 当确保同时曝光的方法或装置（例如机械快门）没有设置MOS成像传感器时，当捕获快速移动的被摄体的静止图像时，运动的被摄体被MOS图像传感器失真，因为成像和读取是 不同时跨MOS传感器。 改变MOS传感器曝光顺序和读取顺序，并插入读取的数据，在对高分辨率运动图像进行成像时，逐行改变读取序列，从而改善移动物体的失真。

    Arithmetic processing apparatus
    136.
    发明申请
    Arithmetic processing apparatus 失效
    算术处理装置

    公开(公告)号：US20050086276A1

    公开(公告)日：2005-04-21

    申请号：US10935193

    申请日：2004-09-08

    申请人： Takashi Masuno ,  Tatsuro Juri

    发明人： Takashi Masuno ,  Tatsuro Juri

    IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F7/544 ,  G06F7/57 ,  G06F15/80 ,  G06F17/10 ,  H04N1/41 ,  H04N7/24 ,  H04N19/00 ,  H04N19/436 ,  H04N19/533 ,  H04N19/625 ,  H04N19/80

    CPC分类号： G06F7/57 ,  G06F7/544 ,  G06F2207/5442 ,  H04N19/42 ,  H04N19/43 ,  H04N19/60 ,  H04N19/61

    摘要： The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.

    摘要翻译： 本发明的算术处理装置是可以根据处理模式重新配置并具有多个排列的单元运算电路的运算处理装置。 每个单元运算电路包括至少一个输入端子，至少一个输出端子，保存数据的第一寄存器，计算两条数据之和的加法器，保存数据的第二寄存器，向左移位数据的位移位器 或右，计算两个数据之间的差的减法器，计算数据的绝对值的绝对值计算单元和根据连接在这些电路元件之间的处理模式设置路径的路径设置单元。

    Variable-length decoding method and apparatus employing code length and a recording medium
    137.
    发明授权
    Variable-length decoding method and apparatus employing code length and a recording medium 失效
    可变长度解码方法和使用码长度的设备和记录介质

    公开(公告)号：US06744928B1

    公开(公告)日：2004-06-01

    申请号：US09380794

    申请日：1999-09-09

    申请人： Tatsuro Juri ,  Tadashi Ono

    发明人： Tatsuro Juri ,  Tadashi Ono

    IPC分类号： G06K936

    CPC分类号： H04N19/88 ,  H04N19/124 ,  H04N19/126 ,  H04N19/13 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/30 ,  H04N19/423 ,  H04N19/60 ,  H04N19/61 ,  H04N19/90 ,  H04N19/91

    摘要： The present invention includes methods and apparatus for attaining high speed coding and decoding. A first method decreases the number of memory access times by performing signal format conversion, orthogonal transform and continuous variable-length coding with predetermined small areas in a frame used as units. A second method omits orthogonal transform computation by using orthogonal transform coefficients to shorten the processing time. A third method uses additions and subtractions for orthogonal transform thereby decreasing the number of registers used and reducing the number of memory access times. The present invention further includes a decoding method for variable-length decoding wherein table size is not made larger because the number of table access times per code word is set to a maximum of 2, and plural code words are decoded by one tale access operation to attain high-speed decoding.

    摘要翻译： 本发明包括用于实现高速编码和解码的方法和装置。 第一种方法是通过执行信号格式转换，正交变换和连续可变长度编码来减少存储器访问次数，并且使用作为单位的帧中的预定小区域进行连续可变长度编码。 第二种方法通过使用正交变换系数来省略正交变换计算，以缩短处理时间。 第三种方法使用加法和减法进行正交变换，从而减少使用的寄存器数量并减少存储器访问次数。 本发明还包括一种用于可变长度解码的解码方法，其中由于每个码字的表访问次数被设置为最大值2，所以不增大表的大小，并且通过一个传播操作将多个码字解码为 达到高速解码。