公开(公告)号：US20230362097A1

公开(公告)日：2023-11-09

申请号：US17990552

申请日：2022-11-18

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Alex Vaynman ,  Roee Moyal ,  Alex Rosenbaum ,  Stanislav Raitsyn ,  Yuval Atias

IPC: H04L47/25 ,  H04L47/22

CPC classification number: H04L47/25 ,  H04L47/22

Abstract: Aspects of the present disclosure are directed to systems, methods, and computer readable media for dynamic data transfer rate control. One method includes alternating a network device between a plurality of supported data transfer rates that are supported by the network device to achieve an unsupported data transfer rate that is not supported by the network device. Another method includes adding one or more dummy work descriptors to a data stream, and transmitting the data stream including the one or more dummy work descriptors at a supported data transfer rate that is supported by a network device to achieve an effective unsupported data transfer rate that is not supported by the network device.

公开(公告)号：US11711158B2

公开(公告)日：2023-07-25

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

CPC classification number: H04J3/0661 ,  H04J3/062

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US11706014B1

公开(公告)日：2023-07-18

申请号：US17579630

申请日：2022-01-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

公开(公告)号：US20230185600A1

公开(公告)日：2023-06-15

申请号：US17549949

申请日：2021-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: G06F9/48 ,  G06F13/16 ,  G06F1/08

CPC classification number: G06F9/4825 ,  G06F9/485 ,  G06F13/1689 ,  G06F1/08

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

公开(公告)号：US11606157B1

公开(公告)日：2023-03-14

申请号：US17520674

申请日：2021-11-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Guy Lederman

IPC: H04J3/06 ,  H04L43/06 ,  H04L43/065 ,  H04L43/067

Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.

公开(公告)号：US20220360423A1

公开(公告)日：2022-11-10

申请号：US17315396

申请日：2021-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Teferet Geula ,  Amit Mandelbaum ,  Ariel Almog

IPC: H04L7/00 ,  H04L12/26 ,  G06N20/00

Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.

公开(公告)号：US20220352998A1

公开(公告)日：2022-11-03

申请号：US17246730

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Roee Moyal ,  Eliel Peretz ,  Eran Ben Elisha ,  Ariel Almog ,  Teferet Geula ,  Amit Mandelbaum

IPC: H04J3/06 ,  H04L12/26 ,  H04L29/08

Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.

公开(公告)号：US11252464B2

公开(公告)日：2022-02-15

申请号：US16850036

申请日：2020-04-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Michael Kagan

IPC: H04N21/00 ,  H04N21/426 ,  G06T1/60

Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

公开(公告)号：US11190462B2

公开(公告)日：2021-11-30

申请号：US16693302

申请日：2019-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis

IPC: G06F15/16 ,  H04L12/939 ,  H04L12/861 ,  H04W28/04 ,  H04L29/06 ,  H04L12/879

Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

公开(公告)号：US11057637B1

公开(公告)日：2021-07-06

申请号：US16775463

申请日：2020-01-29

Applicant: Mellanox Technologies, Ltd. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Tamar Shoham

IPC: H04N19/52 ,  H04N19/177 ,  H04N19/176

Abstract: A video processor includes a memory and a processor. The processor is coupled to memory and is configured to store in the memory (i) multiple raw frames belonging to a Group of Pictures (GOP) to be processed, and (ii) one or more reference frames. The processor is further configured to select for multiple target blocks having a same block-location in respective raw frames associated with a common reference frame, a common search region in the common reference frame, and before selecting another search region, to apply at least two motion estimation operations using at least two of the target blocks and the common search region, to estimate respective at least two Motion Vectors (MVs).