公开(公告)号：US20230206997A1

公开(公告)日：2023-06-29

申请号：US17580178

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

公开(公告)号：US20230186959A1

公开(公告)日：2023-06-15

申请号：US17546431

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

CPC classification number: G11C7/1063

Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

公开(公告)号：US11615008B2

公开(公告)日：2023-03-28

申请号：US17304316

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Fangfang Zhu ,  Murong Lang ,  Zhenming Zhou

IPC: G06F11/00 ,  G06F11/30 ,  G06F12/02 ,  G06F11/07 ,  G11C16/34 ,  G06F11/10

Abstract: An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

公开(公告)号：US20230043775A1

公开(公告)日：2023-02-09

申请号：US17393112

申请日：2021-08-03

Applicant: Micron Technology, Inc.

Inventor： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC: G11C7/20 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/14

Abstract: A system comprising includes a memory device having memory cells a processing device, operatively coupled to the memory device. The processing device is to perform operations including: determining a length of time the memory device has been powered off; and in response to determining that the length of time satisfies a threshold value: for each of multiple groups of memory cells, asserting a corresponding flag; determining, based on the length of time, one or more adjusted demarcation voltages to be used in reading a state of the multiple groups of memory cells; and storing the one or more adjusted demarcation voltages for use in performing memory operations.

公开(公告)号：US20230041421A1

公开(公告)日：2023-02-09

申请号：US17396299

申请日：2021-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

Abstract: Responsive to a power-on of a memory device, an elapsed power-off time is identified based on a difference between a time at which the power-on occurred and a time at which a previous power-off of the memory device occurred. Responsive to a determination that the elapsed power-off time satisfies the elapsed time threshold criterion, a request to perform a first write operation on a memory unit of the memory device since power on is received, a performance parameter associated with the memory unit of the memory device is changed to a first parameter value that corresponds to a reduced performance level, and the write operation is performed on the memory unit of the memory device in accordance with the first parameter value that corresponds to the reduced performance level. Responsive to completion of the write operation, the performance parameter is changed to a value that corresponds to a normal performance level.

公开(公告)号：US20220405181A1

公开(公告)日：2022-12-22

申请号：US17304316

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Fangfang Zhu ,  Murong Lang ,  Zhenming Zhou

IPC: G06F11/30 ,  G06F11/07 ,  G06F12/02

Abstract: An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

公开(公告)号：US11526295B2

公开(公告)日：2022-12-13

申请号：US16934406

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Tingjun Xie ,  Wei Wang ,  Frederick Adi ,  Zhenming Zhou ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A first operating characteristic and a second operating characteristic of a memory sub-system are determined. A write-to-read delay time is set in view of the first operating characteristic and the second operating characteristic. A read operation associated with a memory unit is executed following a period of at least the write-to-read delay time from a time of an execution of a write operation associated with the memory unit.

公开(公告)号：US11307799B2

公开(公告)日：2022-04-19

申请号：US16552165

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.

公开(公告)号：US20220058070A1

公开(公告)日：2022-02-24

申请号：US16996267

申请日：2020-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian HUANG ,  Zhenming ZHOU ,  Zhongguang Xu ,  Murong Lang

IPC: G06F11/07 ,  G06F11/10 ,  G11C16/26

Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

公开(公告)号：US11244740B1

公开(公告)日：2022-02-08

申请号：US16989374

申请日：2020-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C11/34 ,  G11C29/50 ,  G11C29/12 ,  G11C16/10 ,  G11C16/26 ,  G11C29/44

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of the memory sub-system is determined. The value is compared to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied. In response to satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.