中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.017 seconds)

    RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME
    1.
    发明申请
    RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME 有权

    公开(公告)号：US20250086282A1

    公开(公告)日：2025-03-13

    申请号：US18784133

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Lakshmi Kalpana K VAKATI ,  Dheeraj SRINIVASAN ,  Ting LUO ,  Zhenming ZHOU

    IPC: G06F21/57

    Abstract: In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.

    SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINES
    2.
    发明申请
    SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINES 有权

    公开(公告)号：US20250014657A1

    公开(公告)日：2025-01-09

    申请号：US18757422

    申请日：2024-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Ekamdeep SINGH ,  Zhenming ZHOU

    IPC: G11C16/34

    Abstract: In some implementations, a memory device may receive, from a host device, a single-level cell (SLC) program command instructing host data to be written to one or more subblocks of memory. The memory device may determine whether a word line associated with a subblock, of the one or more subblocks, is associated with a reliability risk. The memory device may determine whether to perform a word line leakage monitoring procedure associated with a programming scheme to be used to program the subblock based on whether the word line is associated with the reliability risk.

    MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE
    3.
    发明公开
    MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE 审中-公开

    公开(公告)号：US20240045601A1

    公开(公告)日：2024-02-08

    申请号：US17817465

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Ching-Huang LU ,  Zhenming ZHOU

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

    ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
    4.
    发明申请
    ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES 有权

    公开(公告)号：US20250087277A1

    公开(公告)日：2025-03-13

    申请号：US18784022

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Zhenming ZHOU

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16

    Abstract: In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.

    NAND DETECT EMPTY PAGE SCAN
    5.
    发明公开
    NAND DETECT EMPTY PAGE SCAN 审中-公开

    公开(公告)号：US20240071514A1

    公开(公告)日：2024-02-29

    申请号：US17898043

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Christina PAPAGIANNI ,  Murong LANG ,  Peng ZHANG ,  Zhenming ZHOU

    IPC: G11C16/16 ,  G11C16/08 ,  G11C16/34

    CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/3404 ,  G11C16/3495

    Abstract: A controller of a memory device may identify a plurality of word line groups, included in a block of a memory of the memory device, that include erased pages of the block. The controller may identify a subset of word line groups, of the plurality of word line groups, for a NAND detect empty page (NDEP) scan operation. The controller may perform, based on identifying the subset of word line groups, the NDEP scan operation for the subset of word line groups. A voltage threshold for the NDEP scan may be based on an offset voltage that can be adaptive based on parameters such as quantity of program-erase cycles, memory cell type, and/or operating temperature, among other examples.

    RELIABILITY HEALTH PREDICTION BY HIGH-STRESS SEASONING OF MEMORY DEVICES
    7.
    发明申请
    RELIABILITY HEALTH PREDICTION BY HIGH-STRESS SEASONING OF MEMORY DEVICES 有权

    公开(公告)号：US20220013185A1

    公开(公告)日：2022-01-13

    申请号：US16925222

    申请日：2020-07-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang XU ,  Murong LANG ,  Zhenming ZHOU

    IPC: G11C29/10 ,  G11C29/52

    Abstract: An accelerated seasoning cycle criterion is associated with a memory die of a number of memory dies. The memory die is subjected to one or more accelerated seasoning conditions during accelerated seasoning cycles. Responsive to determining that the accelerated seasoning cycle criterion has been satisfied, a defect scan is performed on the memory die. The memory die is associated with a respective reliability bin of a plurality of reliability bins in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability bin.

    MULTI-FINE PROGRAM SCHEME FOR RELIABILITY RISK WORD LINES
    8.
    发明申请
    MULTI-FINE PROGRAM SCHEME FOR RELIABILITY RISK WORD LINES 有权

    公开(公告)号：US20250103412A1

    公开(公告)日：2025-03-27

    申请号：US18786301

    申请日：2024-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Ching-Huang LU ,  Zhenming ZHOU ,  Jun WAN

    IPC: G06F11/00

    Abstract: In some implementations, a memory device may receive a program command instructing the memory device to program host data to a word line associated with a memory. The memory device may determine a program erase cycle (PEC) count associated with the word line. The memory device may determine, based on the PEC count, a selected program scheme to be used to program the host data to the word line, wherein the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme. The memory device may execute the program command by performing the selected program scheme.

    MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE
    9.
    发明公开
    MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE 审中-公开

    公开(公告)号：US20240256155A1

    公开(公告)日：2024-08-01

    申请号：US18629102

    申请日：2024-04-08

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Ching-Huang LU ,  Zhenming ZHOU

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Patent Agency Ranking