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    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    132.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12230325B2

    公开(公告)日：2025-02-18

    申请号：US17409300

    申请日：2021-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

    IPC: H01L21/768 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    133.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240357818A1

    公开(公告)日：2024-10-24

    申请号：US18760244

    申请日：2024-07-01

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Jordan D. Greenlee

    IPC: H10B43/27 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H10B41/27

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.

    Memories having vertically stacked conductive filled structures
    134.
    发明授权
    Memories having vertically stacked conductive filled structures 有权

    公开(公告)号：US12114492B2

    公开(公告)日：2024-10-08

    申请号：US17071980

    申请日：2020-10-15

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

    IPC: H10B43/27 ,  H01L21/285 ,  H10B41/27 ,  H10B43/10 ,  H10B41/10

    CPC classification number: H10B41/27 ,  H01L21/28562 ,  H10B43/10 ,  H10B43/27 ,  H01L21/28518 ,  H01L21/28568 ,  H10B41/10

    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

    Integrated assemblies and methods of forming integrated assemblies
    138.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US11950416B2

    公开(公告)日：2024-04-02

    申请号：US17164671

    申请日：2021-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

    Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.

    STAIRCASE FORMATION IN A MEMORY ARRAY
    140.
    发明公开
    STAIRCASE FORMATION IN A MEMORY ARRAY 审中-公开

    公开(公告)号：US20240071502A1

    公开(公告)日：2024-02-29

    申请号：US17822712

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

    IPC: G11C16/08 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11578

    CPC classification number: G11C16/08 ,  H01L21/76843 ,  H01L21/76831 ,  H01L21/76885 ,  H01L27/1157 ,  H01L27/11578

    Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).

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