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公开(公告)号：US5287457A
公开(公告)日：1994-02-15
申请号：US870159
申请日：1992-04-15
CPC分类号： G06F13/4027 , G06F13/28
摘要： A DMA controller coupled to two separate buses controls the transfer of data between them. To effect a block data transfer, data is simultaneously read on one bus and written on the other. This allows data to be transferred between buses at the maximum transfer rate supported by the slower bus.
摘要翻译： 耦合到两个独立总线的DMA控制器控制它们之间的数据传输。 为了实现块数据传输，在一个总线上同时读取数据并写入另一个总线。 这允许以较慢总线支持的最大传输速率在总线之间传输数据。
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公开(公告)号：US5109490A
公开(公告)日：1992-04-28
申请号：US297772
申请日：1989-01-13
CPC分类号： G06F13/4217 , G06F13/28
摘要： A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.
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133.发明授权Data processing system and method for reducing cache pollution by write stream memory access patterns 有权用于通过写入流存储器访问模式减少高速缓存污染的数据处理系统和方法公开(公告)号：US08909871B2
公开(公告)日：2014-12-09
申请号：US11462115
申请日：2006-08-03
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译： 数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。 根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。 确定存储修改操作是否具有相关的旁路指示。 响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。 响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。
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公开(公告)号：US08775778B2
公开(公告)日：2014-07-08
申请号：US12024228
申请日：2008-02-01
IPC分类号： G06F9/30
CPC分类号： G06F9/544 , G06F9/4843
摘要： A set of helper thread binaries is created from a set of main thread binaries. The helper thread monitors software or hardware ports for incoming data events. When the helper thread detects an incoming event, the helper thread asynchronously executes instructions that calculate incoming data needed by the main thread.
摘要翻译： 一组辅助线程二进制文件是从一组主线程二进制文件创建的。 辅助线程监视输入数据事件的软件或硬件端口。 当辅助线程检测到传入事件时，辅助线程异步执行计算主线程所需的传入数据的指令。
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公开(公告)号：US20130179899A1
公开(公告)日：2013-07-11
申请号：US12342559
申请日：2008-12-23
申请人： Ravi K. Arimilli , Piyush Chaudhary
发明人： Ravi K. Arimilli , Piyush Chaudhary
IPC分类号： G06F9/54
摘要： A mechanism is provided for managing a process-to-process communication request. A call is received in an operating system from an application in the data processing system. The operating system passes the call to a host fabric interface controller in the data processing system without processing the call. The host fabric interface controller processes the call using state information associated with the call. The call is processed by the host fabric interface controller without intervention by the operating system.
摘要翻译： 提供了一种用于管理进程到进程通信请求的机制。 在来自数据处理系统中的应用的操作系统中接收到呼叫。 操作系统将呼叫传递到数据处理系统中的主机结构接口控制器，而不处理该呼叫。 主机结构接口控制器使用与呼叫相关联的状态信息来处理呼叫。 呼叫由主机结构接口控制器处理，无需操作系统的干预。
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公开(公告)号：US08356151B2
公开(公告)日：2013-01-15
申请号：US12024504
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/30043 , G06F12/0831 , G06F12/0862 , G06F12/1027
摘要： A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for completion of the physical movement of data from a first memory location to a second memory location. The processor executes a second operation, which checks a status of the completion of the data move and returns a notification indicating the status. The notification indicates a status, which includes one of: data move in progress; data move totally done; data move partially done; data move cannot be performed; and occurrence of a translation look-aside buffer invalidate entry (TLBIE) operation. The processor initiates one or more actions in response to the notification received.
摘要翻译： 在数据处理系统中执行的方法启动异步存储器移动（AMM）操作，由此处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并将AMM操作的参数转发到异步存储器 用于完成数据从第一存储器位置到第二存储器位置的物理移动的移动器逻辑。 处理器执行第二操作，其检查数据移动完成的状态，并返回指示状态的通知。 该通知表示状态，其中包括：数据移动进行中的一个; 数据移动完成; 数据移动部分完成; 无法执行数据移动; 以及出现翻译后备缓冲区无效条目（TLBIE）操作。 处理器响应于收到的通知发起一个或多个动作。
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公开(公告)号：US20120304201A1
公开(公告)日：2012-11-29
申请号：US13444276
申请日：2012-04-11
申请人： Ravi K. Arimilli , Piyush Chaudhary
发明人： Ravi K. Arimilli , Piyush Chaudhary
IPC分类号： G06F9/54
摘要： A mechanism is provided for managing a process-to-process communication request. A call is received in an operating system from an application in the data processing system. The operating system passes the call to a host fabric interface controller in the data processing system without processing the call. The host fabric interface controller processes the call using state information associated with the call. The call is processed by the host fabric interface controller without intervention by the operating system.
摘要翻译： 提供了一种用于管理进程到进程通信请求的机制。 在来自数据处理系统中的应用的操作系统中接收到呼叫。 操作系统将呼叫传递到数据处理系统中的主机结构接口控制器，而不处理该呼叫。 主机结构接口控制器使用与呼叫相关联的状态信息来处理呼叫。 呼叫由主机结构接口控制器处理，无需操作系统的干预。
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138.发明申请Performing Setup Operations for Receiving Different Amounts of Data While Processors are Performing Message Passing Interface Tasks 审中-公开在处理器执行消息传递接口任务时，执行接收不同数据量的设置操作公开(公告)号：US20120266180A1
公开(公告)日：2012-10-18
申请号：US13524585
申请日：2012-06-15
IPC分类号： G06F9/52 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译： 提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。 提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。
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139.发明授权Mechanisms for communicating with an asynchronous memory mover to perform AMM operations 有权与异步存储器移动器进行通信以执行AMM操作的机制公开(公告)号：US08245004B2
公开(公告)日：2012-08-14
申请号：US12024560
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system includes a set of architected registers within which the processor places state and other information to communicate with the asynchronous memory mover in order to initiate and control an AMM operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation in response to receiving a set of parameters within the architected registers, which parameters are associated with an AMM store instruction executed by the processor to initiates a move of data in virtual space before placing the information in the architected registers. The architected registers are processor architected registers, defined on a per thread basis by a compiler, or memory mapped architected registers allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application. The architected registers are also utilized to store state information to enable a restore to a point before execution of the AMM operation.
摘要翻译： 数据处理系统包括一组架构寄存器，处理器将处理器置于与异步存储器移动器通信的状态和其它信息，以启动和控制AMM操作。 异步存储器移动器响应于在结构化寄存器内接收到一组参数而执行异步存储器移动（AMM）操作，哪些参数与处理器执行的AMM存储指令相关联，以在放置之前启动虚拟空间中的数据移动 建筑登记册中的信息。 架构寄存器是由编译器在每个线程基础上定义的处理器架构寄存器，或者在应用程序的绑定和后续执行期间分配用于与异步存储器移动器进行通信的内存映射架构寄存器。 架构寄存器还用于存储状态信息，以便在执行AMM操作之前恢复到一个点。
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140.发明申请Dynamic Monitoring of Ability to Reassemble Streaming Data Across Multiple Channels Based on History 有权基于历史，跨多个渠道重组流数据的能力的动态监测公开(公告)号：US20120191674A1
公开(公告)日：2012-07-26
申请号：US13438227
申请日：2012-04-03
申请人： Ravi K. Arimilli , Piyush Chaudhary
发明人： Ravi K. Arimilli , Piyush Chaudhary
IPC分类号： G06F17/30
CPC分类号： H04L1/1841 , G06F9/546 , H04L69/14
摘要： Mechanisms are provided for processing streaming data at high sustained data rates. These mechanisms receive a plurality of data elements over a plurality of non-sequential communication channels and write the plurality of data elements directly to the file system of the data processing system in an unassembled manner. The mechanisms determining whether to perform a data scrubbing operation or not based on history information indicative of whether data elements in the plurality of data elements are being received in a substantially sequential manner. The mechanisms perform a data scrubbing operation, in response to a determination to perform data scrubbing, to identify any missing data elements in the plurality of data elements written to the tile system and assemble the plurality of data elements into a plurality of data streams in response to results of the data scrubbing indicating that there are no missing data elements.
摘要翻译： 提供了用于以高持续数据速率处理流数据的机制。 这些机制通过多个非顺序通信信道接收多个数据元素，并以未组装的方式将多个数据元素直接写入数据处理系统的文件系统。 基于表示多个数据元素中的数据元素是否以大致顺序的方式被接收的历史信息，确定是否执行数据擦除操作的机制。 响应于执行数据擦除的确定，机构执行数据擦除操作以识别写入瓦片系统的多个数据元素中的任何丢失的数据元素，并将多个数据元素组合成多个数据流以作为响应 到数据清理的结果，表明没有丢失的数据元素。
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