公开(公告)号：US20200007168A1

公开(公告)日：2020-01-02

申请号：US16568221

申请日：2019-09-11

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: H03M13/29 ,  H03M13/09 ,  H03M13/13

Abstract: A data storage system includes a processing circuit, a calculating circuit and an encoding circuit. The processing circuit receives a data byte from a host. The calculating circuit generates a cyclic redundancy check code according to an LBA, and combines the cyclic redundancy check code and the data byte into a data sector so that the data sector includes LBA-related information. The encoding circuit encodes the data sector to generate an error checking and correcting code, and combines the data sector and the error checking and correcting code into a storage data, so that the storage data includes the LBA-related information without including the LBA. Via the data sector and the storage data, the data storage system performs cyclic redundancy checking as well as error checking and correcting without storing the LBA for reducing 1-bit errors; and the LBA-related information does not include part or all of the LBA.

公开(公告)号：US10324786B2

公开(公告)日：2019-06-18

申请号：US15717970

申请日：2017-09-28

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Li-Sheng Kan

IPC: G06F11/10 ,  G06F3/00 ,  G06F11/14 ,  G06F12/02

Abstract: A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result.

公开(公告)号：US20190173492A1

公开(公告)日：2019-06-06

申请号：US16251033

申请日：2019-01-17

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/09 ,  G11C11/56 ,  H03M13/15 ,  G06F11/10 ,  G11C16/10 ,  H03M13/00

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US20190121756A1

公开(公告)日：2019-04-25

申请号：US16053764

申请日：2018-08-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F13/16 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F13/1668 ,  G06F11/1004 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/108 ,  G11C29/52

Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.

公开(公告)号：US20190050326A1

公开(公告)日：2019-02-14

申请号：US16159723

申请日：2018-10-15

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F12/02 ,  G06F11/10 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C7/10 ,  G11C29/52 ,  G11C16/04

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.

公开(公告)号：US20180373593A1

公开(公告)日：2018-12-27

申请号：US16115570

申请日：2018-08-29

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/56 ,  G11C29/52 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: A method for accessing a flash memory module includes: sequentially writing Nth−(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth−(N+K)th data to generate Nth−(N+K)th ECCs, respectively, where the Nth−(N+K)th ECCs are used to correct errors of the Nth−(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth−(N+K)th ECCs to generate the (N+K+1)th ECC.

公开(公告)号：US10164656B2

公开(公告)日：2018-12-25

申请号：US15086006

申请日：2016-03-30

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Jian-Dong Du

IPC: H03M13/11 ,  H03M13/37 ,  H03M13/45

Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.

公开(公告)号：US10163499B2

公开(公告)日：2018-12-25

申请号：US15431643

申请日：2017-02-13

Applicant: Silicon Motion Inc.

Inventor： Ching-Hui Lin ,  Tsung-Chieh Yang

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: A control device for writing data into a flash memory unit includes a determining circuit and a writing circuit. The determining circuit is arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time. The writing circuit is arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only. The determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time. The writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only.

公开(公告)号：US10153048B2

公开(公告)日：2018-12-11

申请号：US15672318

申请日：2017-08-09

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/34 ,  H03M13/15

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US10049005B2

公开(公告)日：2018-08-14

申请号：US15666569

申请日：2017-08-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: A flash memory control apparatus includes a data read/write interface and a controller. The data read/write interface is arranged for coupling a first flash memory and a second flash memory, wherein the first flash memory includes a first storage plane and a first buffer, and the second flash memory includes a second storage plane and a second buffer. The controller is coupled to the data read/write interface, and is arranged for transmitting a plurality of valid data sets stored in the first storage plane to the second buffer through the data read/write interface. After an erase cycle is performed on the first storage plane, the controller further programs the plurality of valid data sets transmitted to the second buffer into the first storage plane.