公开(公告)号：US07982496B1

公开(公告)日：2011-07-19

申请号：US12417012

申请日：2009-04-02

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1733

摘要： A bus-based logic block for an integrated circuit includes a provision for placing an arbitrary constant onto a data bus in the logic block. An exemplary logic block has multi-bit first and second inputs and a multi-bit output. The logic block includes a multi-bit multiplexer circuit, a multi-bit programmable logic circuit, and a constant generator circuit. The multiplexer circuit has a multi-bit first input coupled to a multi-bit first input of the logic block, a multi-bit second input, and a multi-bit output. The programmable logic circuit has a multi-bit first input coupled to the output of the multiplexer circuit, and a multi-bit output. The constant generator circuit has a multi-bit output coupled to the second input of the multiplexer circuit. Each bit of the logic block may be commonly controlled with all other bits of the logic block.

摘要翻译： 用于集成电路的基于总线的逻辑块包括用于将任意常数放置在逻辑块中的数据总线上的规定。 示例性的逻辑块具有多位第一和第二输入和多位输出。 逻辑块包括多位多路复用器电路，多位可编程逻辑电路和恒定的发生器电路。 多路复用器电路具有耦合到逻辑块的多位第一输入，多位第二输入和多位输出的多位第一输入。 可编程逻辑电路具有耦合到多路复用器电路的输出的多位第一输入和多位输出。 恒定发电机电路具有耦合到多路复用器电路的第二输入的多位输出。 逻辑块的每个位可以与逻辑块的所有其他位共同地被控制。

公开(公告)号：US07948265B1

公开(公告)日：2011-05-24

申请号：US12417051

申请日：2009-04-02

申请人： Steven P. Young ,  Brian C. Gaide

发明人： Steven P. Young ,  Brian C. Gaide

IPC分类号： H03K19/173

CPC分类号： H03K19/0966 ,  H03K19/173

摘要： Circuits for implementing logic replication in self-timed integrated circuits are provided. An exemplary circuit includes first and second copies of a replicated circuit, an input circuit, an output circuit, and a pipelined routing path. The first and second copies each have a self-timed input and a self-timed output. The input circuit provides a self-timed input signal alternately to the self-timed inputs of the first and second copies. The output circuit receives the self-timed output from the first copy and the self-timed output from the second copy, and outputs a selected one of the self-timed outputs based on a value of a self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit. The number of pipeline stages in the pipelined routing path can be different from, e.g., less than, the number of stages in both the first and second copies.

摘要翻译： 提供了在自定时集成电路中实现逻辑复制的电路。 示例性电路包括复制电路的第一和第二副本，输入电路，输出电路和流水线路由路径。 第一和第二副本每个都具有自定时输入和自定时输出。 输入电路将自定时输入信号交替地提供给第一和第二副本的自定时输入。 输出电路接收来自第一拷贝的自定时输出和来自第二拷贝的自定时输出，并且基于自定时选择信号的值输出所选择的一个自定时输出。 流水线路由路径将自定时选择信号从输入电路路由到输出电路。 流水线路由路径中的流水线级数可以不同于例如小于第一和第二副本中的级数。

公开(公告)号：US07746105B1

公开(公告)日：2010-06-29

申请号：US12417036

申请日：2009-04-02

申请人： Brian C. Gaide ,  Steven P. Young

发明人： Brian C. Gaide ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  H03K19/17736

摘要： Circuits for merging data streams in a self-timed programmable integrated circuit. A programmable integrated circuit includes interconnected logic blocks, each including a logic circuit and an output multiplexer circuit including an arbiter and a multiplexer. Each arbiter is coupled to receive ready signals provided with first and second outputs of the logic circuit. Each multiplexer has first and second data inputs coupled to the outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes, to an arbiter output, and a data output coupled to an output of the logic block. The output multiplexer circuit provides an output token only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on one of the data inputs, and stores a third token received on the other data input until the other data input is selected by the multiplexer.

摘要翻译： 用于在自定时可编程集成电路中合并数据流的电路。 可编程集成电路包括互连的逻辑块，每个逻辑块包括逻辑电路和包括仲裁器和复用器的输出多路复用器电路。 每个仲裁器被耦合以接收提供有逻辑电路的第一和第二输出的就绪信号。 每个多路复用器具有耦合到逻辑电路的输出的第一和第二数据输入，以多个操作模式中的一个可编程地耦合到仲裁器输出的可选择输入以及耦合到逻辑块的输出的数据输出。 输出多路复用器电路仅在第一个令牌表示仲裁器输出上的有效新数据并且第二个令牌在其中一个数据输入上指示有效的新数据时才提供输出令牌，并且存储在另一个数据输入上接收的第三个令牌，直到另一个 数据输入由多路复用器选择。

公开(公告)号：US07746103B1

公开(公告)日：2010-06-29

申请号：US12417020

申请日：2009-04-02

申请人： Brian C. Gaide ,  Steven P. Young

发明人： Brian C. Gaide ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： G06F7/53 ,  G06F2207/3864

摘要： A multi-mode circuit for a self-timed integrated circuit is provided. The multi-mode circuit is programmable to operate in two or more modes, and is coupled to require, in each mode, receipt of a token on at least one of first, second, or third inputs before providing an output token. The multi-mode circuit is further coupled to require tokens on different inputs in at least two different modes. The multi-mode circuit can be an output circuit for a logic block in an integrated circuit including an array of interconnected logic blocks, where each logic block includes a logic circuit and a multi-mode circuit. One input of each multi-mode circuit can be programmably coupled to a select output of a multi-mode circuit in an adjacent logic block. Based on the programmed mode and the tokens received, the circuit routes data between inputs and outputs of the circuit.

摘要翻译： 提供了一种用于自定时集成电路的多模电路。 多模式电路可编程以在两种或更多种模式下操作，并且耦合以在提供输出令牌之前在每种模式中要求在第一，第二或第三输入中的至少一个上接收令牌。 多模电路还被耦合以在至少两种不同模式中的不同输入上要求令牌。 多模电路可以是包括互连逻辑块阵列的集成电路中的逻辑块的输出电路，其中每个逻辑块包括逻辑电路和多模电路。 每个多模电路的一个输入可以可编程地耦合到相邻逻辑块中的多模电路的选择输出。 基于接收的编程模式和令牌，电路在数据输入和输出之间路由数据。

公开(公告)号：US07724016B2

公开(公告)日：2010-05-25

申请号：US12355988

申请日：2009-01-19

申请人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

发明人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

IPC分类号： G01R31/02

CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

公开(公告)号：US07635989B1

公开(公告)日：2009-12-22

申请号：US12174926

申请日：2008-07-17

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： G06F15/7867 ,  H03K19/17736 ,  H03K19/20

摘要： Integrated circuits (ICs) having bus-based programmable interconnect structures are provided. An IC includes substantially similar logic blocks and a programmable interconnect structure programmably interconnecting the logic blocks. The programmable interconnect structure includes bus structures and programmable switching structures programmably interconnecting the bus structures. Each bus structure includes N data lines, where N is an integer greater than one, and N commonly controlled storage elements (e.g., latches) for storing data on the N data lines. In some embodiments, at least one of the bus structures includes handshake logic, including a C-element coupled to drive a ready line, to receive an acknowledge line, and to provide a control signal to each of the N storage elements in the bus structure. In some embodiments, each of the programmable switching structures includes N M-input data multiplexers, an M-input ready multiplexer, and an M-output acknowledge demultiplexer, M being an integer greater than one.

摘要翻译： 提供了具有基于总线的可编程互连结构的集成电路（IC）。 IC包括基本相似的逻辑块和可编程互连结构，可编程地互连逻辑块。 可编程互连结构包括可编程地互连总线结构的总线结构和可编程开关结构。 每个总线结构包括N个数据线，其中N是大于1的整数，以及N个用于在N个数据线上存储数据的通常受控的存储元件（例如，锁存器）。 在一些实施例中，总线结构中的至少一个包括握手逻辑，包括耦合以驱动就绪线的C元件，以接收确认线，并且向总线结构中的每个N个存储元件提供控制信号 。 在一些实施例中，每个可编程切换结构包括N M个输入数据多路复用器，M输入就绪复用器和M输出确认解复用器，M是大于1的整数。

公开(公告)号：US07557610B2

公开(公告)日：2009-07-07

申请号：US11581914

申请日：2006-10-17

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： G06F7/38 ,  H03K19/173 ,  H01L25/00 ,  H03K19/00

CPC分类号： H01L27/11898 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11807

摘要： An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

摘要翻译： FPGA被布置为多个可重复的瓦片，其中瓦片设置在从管芯的一侧延伸到管芯的另一侧的列中，并且其中每个列包括主要为一种类型的瓦片。 因为柱的基本上所有的模具区域都是由于单一类型的瓦片，所以每列的瓦片的宽度可被优化，并且在很大程度上独立于模具上的其它类型的瓦片的尺寸。 因此，可以将每种类型的瓦片的限制设置为与瓦片的电路的尺寸相匹配。 围绕芯片周边提供输入/输出块（IOB）的环，而不是I列。 如果需要两列以上的IOB，则可以提供两列以上的IOB图块。

公开(公告)号：US07518401B2

公开(公告)日：2009-04-14

申请号：US11511973

申请日：2006-08-29

申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

IPC分类号： H01L25/00 ,  H03K19/177 ,  H03K19/00

CPC分类号： G06F1/10 ,  H03K5/2481

摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

摘要翻译： 一种时钟分配网络，具有：主干线，其被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

公开(公告)号：US07498192B1

公开(公告)日：2009-03-03

申请号：US11334341

申请日：2006-01-17

申请人： F. Erich Goetting ,  Trevor J. Bauer ,  Patrick J. McGuire ,  Bruce E. Talley ,  Paul Ying-Fung Wu ,  Steven P. Young

发明人： F. Erich Goetting ,  Trevor J. Bauer ,  Patrick J. McGuire ,  Bruce E. Talley ,  Paul Ying-Fung Wu ,  Steven P. Young

IPC分类号： H01L21/44

CPC分类号： H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.

摘要翻译： 制造具有至少两个不同逻辑容量的封装集成电路（IC）系列的方法。 第一IC芯片包括两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。 第一组第一IC芯片被封装成使得模具的两个部分都可操作。 封装第一组IC芯片，使得只有每个裸片的第一部分可操作。 一旦封装了第一组和第二组，并且已经评估了第二组IC，则决定是否制造包括第一模具的第一部分的第二IC模具，同时排除第二部分。

公开(公告)号：US07480690B2

公开(公告)日：2009-01-20

申请号：US11019854

申请日：2004-12-21

申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

IPC分类号： G06F7/48

CPC分类号： G06F7/509

摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

摘要翻译： 描述的是算术电路，逻辑上分为乘积发生器和加法器。 逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。 还可以控制复用电路以将多个外部添加的输入引导到加法器。 附加加数输入可以包括从其他算术电路级联的输入和输出。