公开(公告)号：US20220328457A1

公开(公告)日：2022-10-13

申请号：US17853524

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/552 ,  H01L21/3205 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

公开(公告)号：US11417580B2

公开(公告)日：2022-08-16

申请号：US17012299

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Hsin Wei ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Hsien-Pin Hu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L23/16 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

公开(公告)号：US20220157695A1

公开(公告)日：2022-05-19

申请号：US17588920

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.

公开(公告)号：US11270976B2

公开(公告)日：2022-03-08

申请号：US16454098

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Hang Liao ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

公开(公告)号：US11164852B2

公开(公告)日：2021-11-02

申请号：US16272973

申请日：2019-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/11 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/66 ,  H01L21/56 ,  H01L23/427 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

公开(公告)号：US20210327816A1

公开(公告)日：2021-10-21

申请号：US17360313

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

公开(公告)号：US11069673B2

公开(公告)日：2021-07-20

申请号：US16886795

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/10 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/50 ,  H01L23/498 ,  H01L21/60

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

公开(公告)号：US20210125964A1

公开(公告)日：2021-04-29

申请号：US17140791

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

公开(公告)号：US20210005464A1

公开(公告)日：2021-01-07

申请号：US17026712

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/66

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

公开(公告)号：US20200350279A1

公开(公告)日：2020-11-05

申请号：US16933593

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/78 ,  H01L23/31

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.