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    Integrated circuits with buried interconnect conductors
    133.
    发明授权
    Integrated circuits with buried interconnect conductors 有权

    公开(公告)号：US10998238B2

    公开(公告)日：2021-05-04

    申请号：US16288636

    申请日：2019-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L21/70 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088

    Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

    Semiconductor device and manufacturing method thereof
    134.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10950714B2

    公开(公告)日：2021-03-16

    申请号：US16714532

    申请日：2019-12-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Keng-Chu Lin ,  Shi-Ning Ju

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762

    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin, a gate structure, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin and a second semiconductor fin extend upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The shallow trench isolation (STI) oxide has a horizontal portion extending along a top surface of the substrate and vertical portions extending upwardly from the horizontal portion along the first and second semiconductor fins. The dielectric layer has a horizontal portion extending along a top surface of the horizontal portion of the STI oxide and vertical portions extending upwardly from the horizontal portion of the dielectric layer to a position higher than top ends of the vertical portions of the STI oxide.

    Integrated circuits with backside power rails
    135.
    发明授权
    Integrated circuits with backside power rails 有权

    公开(公告)号：US10833003B1

    公开(公告)日：2020-11-10

    申请号：US16427831

    申请日：2019-05-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chao Chou ,  Kuo-Cheng Ching ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

    IPC: H01L23/50 ,  H01L27/088 ,  H01L29/78

    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

    Etch Profile Control of Polysilicon Structures of Semiconductor Devices
    136.
    发明申请
    Etch Profile Control of Polysilicon Structures of Semiconductor Devices 审中-公开

    公开(公告)号：US20200279778A1

    公开(公告)日：2020-09-03

    申请号：US16877345

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Ting Pan

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238

    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively

    Fin isolation structures of semiconductor devices
    138.
    发明授权
    Fin isolation structures of semiconductor devices 有权

    公开(公告)号：US10714394B2

    公开(公告)日：2020-07-14

    申请号：US15718752

    申请日：2017-09-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Yen-Ming Chen

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762

    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

    Etch profile control of polysilicon structures of semiconductor devices
    140.
    发明授权
    Etch profile control of polysilicon structures of semiconductor devices 有权

    公开(公告)号：US10658245B2

    公开(公告)日：2020-05-19

    申请号：US16246209

    申请日：2019-01-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Ting Pan

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51

    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively.

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