公开(公告)号：US20210225654A1

公开(公告)日：2021-07-22

申请号：US17203306

申请日：2021-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yasutoshi Okuno ,  Teng-Chun Tsai ,  Ziwei Fang ,  Fu-Ting Yen

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

公开(公告)号：US20210183858A1

公开(公告)日：2021-06-17

申请号：US16717433

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

Abstract: An Integrated Circuit (IC) device includes a first plurality of semiconductor layers over a substrate, a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first fill metal layer and a work function metal layer disposed between the first gate dielectric layer and the first fill metal layer. The IC device further includes a second plurality of semiconductor layers over the substrate, a second gate dielectric layer and a second gate electrode. The second gate electrode includes a second fill metal layer directly contacting the second gate dielectric layer. A top surface of the second fill metal layer extends above a topmost layer of the second plurality of semiconductor layers. The material of the semiconductor layers has a midgap. The work function metal layer has a work function lower than the midgap. The fill metal layer has a work function higher than the midgap.

公开(公告)号：US11007005B2

公开(公告)日：2021-05-18

申请号：US15988624

申请日：2018-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Ziwei Fang ,  Yee-Chia Yeo ,  Meng-Hsuan Hsiao

IPC: A61B18/14 ,  A61B17/295 ,  A61B17/29 ,  A61B17/285 ,  A61B17/28 ,  A61B90/00 ,  H01L29/417 ,  H01L29/78 ,  A61B18/00

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US10978567B2

公开(公告)日：2021-04-13

申请号：US16573498

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.

公开(公告)号：US20210082918A1

公开(公告)日：2021-03-18

申请号：US16573866

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

公开(公告)号：US10923393B2

公开(公告)日：2021-02-16

申请号：US16297117

申请日：2019-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

Abstract: A first conductive feature has a dielectric layer formed thereover. An opening is formed in the dielectric layer to expose a portion of the first conductive feature. A first barrier layer is formed over the first conductive feature and over a top surface of the dielectric layer. A second barrier layer is formed over the first barrier layer and on sidewalls of the opening. The second barrier layer is removed, resulting in at least a portion of the first barrier layer disposed over the first conductive feature. A second conductive feature is formed over the portion of the first barrier layer. Sidewalls of the second conductive feature directly contact the dielectric layer.

公开(公告)号：US20210036127A1

公开(公告)日：2021-02-04

申请号：US16526650

申请日：2019-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING , CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Ziwei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.

公开(公告)号：US20200373400A1

公开(公告)日：2020-11-26

申请号：US16690645

申请日：2019-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Ziwei Fang ,  Chun-I WU ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US20200350430A1

公开(公告)日：2020-11-05

申请号：US16933255

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Sheng-Wen Yu ,  Ziwei Fang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

公开(公告)号：US10431670B2

公开(公告)日：2019-10-01

申请号：US15481211

申请日：2017-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu ,  Ziwei Fang

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/167 ,  H01L29/08

Abstract: Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (SPD) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the source region and the drain region of fin structure. In some implementations, the SPD layer is disposed over the fin structure, such that the dopant diffuses laterally and vertically into the source region and the drain region to form heavily doped source/drain features.