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公开(公告)号：US09348642B2
公开(公告)日：2016-05-24
申请号：US13524845
申请日：2012-06-15
CPC分类号： G06F9/467 , G06F9/30025 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/45558 , G06F9/5077 , G06F9/528
摘要： A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. A constrained transaction has one or more restrictions associated therewith, while a nonconstrained transaction is not limited in the manner of a constrained transaction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.
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公开(公告)号：US09286065B2
公开(公告)日：2016-03-15
申请号：US13421640
申请日：2012-03-15
摘要： The length of character data having a termination character is determined. The character data for which the length is to be determined is loaded, in parallel, within one or more vector registers. An instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded, using, for instance, another instruction. Further, an instruction is used to find the index of the first termination character, e.g., the first zero or null character. This instruction searches the data in parallel for the termination character. By using these instructions, the length of the character data is determined using only one branch instruction.
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133.发明授权公开(公告)号：US09286064B2
公开(公告)日：2016-03-15
申请号：US13421498
申请日：2012-03-15
摘要： Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character data to be copied is loaded within one or more vector registers. In particular, in one embodiment, an instruction (e.g., a Vector Load to block Boundary instruction) is used that loads data in parallel in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. To determine the number of characters loaded (a count), another instruction (e.g., a Load Count to Block Boundary instruction) is used. Further, an instruction (e.g., a Vector Find Element Not Equal instruction) is used to find the index of the first delimiter character, i.e., the first termination character, such as a zero or null character within the character data. This instruction checks a plurality of bytes of data in parallel.
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公开(公告)号：US09158660B2
公开(公告)日：2015-10-13
申请号：US13422546
申请日：2012-03-16
申请人： Mark S. Farrell , Charles W. Gainey, Jr. , Marcel Mitran , Chung-Lung K. Shum , Timothy J. Slegel , Brian L. Smith , Kevin A. Stoodley
发明人： Mark S. Farrell , Charles W. Gainey, Jr. , Marcel Mitran , Chung-Lung K. Shum , Timothy J. Slegel , Brian L. Smith , Kevin A. Stoodley
IPC分类号： G06F11/36
CPC分类号： G06F11/3644 , G06F9/30076 , G06F9/30101 , G06F11/3636 , G06F11/3648
摘要： An aspect includes enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. The instruction is executed based on determining, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.
摘要翻译： 一个方面包括启用和禁用运行时仪器设施的执行。 处理器处于较低特权状态的执行指令由处理器提取。 该指令是基于由处理器确定运行时仪表设备允许执行较弱特权状态的指令并且与运行时仪表设备相关联的控制是有效的而执行的。 基于运行时间仪器设备（RIOFF）指令的指令，运行时仪表设备被禁用。 禁用包括更新处理器的程序状态字（PSW）中的位以指示运行时仪表数据不应被处理器捕获。 基于（RION）指令的运行时仪表设备的指令启用运行时仪表设备。 启用包括更新PSW中的位以指示运行时仪表数据应由处理器捕获。
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公开(公告)号：US09146739B2
公开(公告)日：2015-09-29
申请号：US13517779
申请日：2012-06-14
申请人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
发明人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
CPC分类号： G06F9/30058 , G06F9/3806 , G06F9/3844
摘要： Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.
摘要翻译： 实施例涉及分支预测预加载。 一方面包括用于分支预测预加载的系统。 该系统包括耦合到处理电路的指令高速缓存和分支目标缓冲器（BTB），所述处理电路被配置为执行方法。 该方法包括从指令高速缓冲存储器中取出指令流中的多个指令，以及对指令流中的分支预测预加载指令进行解码。 基于分支预测预加载指令来确定预测分支指令的地址。 基于分支预测预加载指令来确定预测目标地址。 在分支预测预加载指令中识别掩码字段，并且基于掩码字段来确定分支指令长度。 基于执行分支预测预加载指令，BTB预先加载预测分支指令的地址，分支指令长度，分支类型和预测目标地址。
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公开(公告)号：US08966324B2
公开(公告)日：2015-02-24
申请号：US13524779
申请日：2012-06-15
IPC分类号： G06F11/00
CPC分类号： G06F9/30058 , G06F9/30087 , G06F9/466 , G06F11/366
摘要： Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure.
摘要翻译： 当事务被中止时，事务执行分支指示被放置到一个或多个事务诊断块中。 作为在事务中执行分支指令的结果，每个分支指示指定是否采用分支。 当事务执行并且遇到分支指令时，在指示是否采取分支的向量中设置分支指示。 然后，如果事务中止，则指示符存储在提供可用于诊断故障的分支历史的一个或多个事务诊断块中。
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137.发明授权High-word facility for extending the number of general purpose registers available to instructions 有权用于扩展可用于指令的通用寄存器数量的高位设备公开(公告)号：US08914619B2
公开(公告)日：2014-12-16
申请号：US12820735
申请日：2010-06-22
申请人： Dan F. Greiner , Marcel Mitran , Timothy J. Slegel
发明人： Dan F. Greiner , Marcel Mitran , Timothy J. Slegel
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30105 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/322 , G06F9/342
摘要： A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed.
摘要翻译： 计算机采用一组通用寄存器（GPR）。 每个GPR包括多个部分。 诸如操作系统和以大GPR模式运行的应用程序等程序可访问完整的GPR，但是以小GPR模式运行的应用程序等程序只能一次访问一部分。 指令操作码，在小GPR模式下，可以确定访问哪个部分。
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公开(公告)号：US08682877B2
公开(公告)日：2014-03-25
申请号：US13524788
申请日：2012-06-15
CPC分类号： G06F9/467 , G06F9/30076 , G06F9/3861
摘要： Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt.
摘要翻译： 提供约束事务处理。 受约束的事务通过执行Transaction Begin约束指令来启动。 受约束的事务具有与其相关联的许多限制。 没有违反限制，受约束的交易即将完成。 如果遇到中止条件，则从事务开始指令开始重新执行事务。 违反限制可能会导致中断。
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公开(公告)号：US20130339796A1
公开(公告)日：2013-12-19
申请号：US13524779
申请日：2012-06-15
CPC分类号： G06F9/30058 , G06F9/30087 , G06F9/466 , G06F11/366
摘要： Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure.
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公开(公告)号：US20130339684A1
公开(公告)日：2013-12-19
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.
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