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    SEPARATION AND EXTRACTION SYSTEM
    131.
    发明申请
    SEPARATION AND EXTRACTION SYSTEM 审中-公开
    分离和萃取系统

    公开(公告)号：US20090090894A1

    公开(公告)日：2009-04-09

    申请号：US11868355

    申请日：2007-10-05

    Applicant: Bin Wang ,  Hao Feng ,  Thaddeus Ezeji ,  Hans Blaschek

    Inventor： Bin Wang ,  Hao Feng ,  Thaddeus Ezeji ,  Hans Blaschek

    IPC: B01D11/04

    CPC classification number: B01D11/0492 ,  C07C253/34 ,  C07C255/03

    Abstract: Extraction systems comprising acetonitrile, water, and a saccharide selected from the group consisting of a monosaccharide, an oligosaccharide, and mixtures thereof. The systems comprise a first phase and a second phase, and the concentration of the saccharide is at least 0.5 weight/volume %.

    Abstract translation: 包含乙腈，水和选自单糖，低聚糖及其混合物的糖类的提取系统。 该系统包括第一相和第二相，糖的浓度为至少0.5重量/体积％。

    High voltage FET gate structure
    133.
    发明授权
    High voltage FET gate structure 有权
    高压FET栅极结构

    公开(公告)号：US07375398B2

    公开(公告)日：2008-05-20

    申请号：US11138888

    申请日：2005-05-26

    Applicant: Bin Wang ,  Chih-Hsin Wang

    Inventor： Bin Wang ,  Chih-Hsin Wang

    IPC: H01L23/62

    CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

    Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

    Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。 这样，第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。

    Method of subsalt velocity analysis by combining wave equation based redatuming and kirchhoff based migration velocity analysis
    134.
    发明申请
    Method of subsalt velocity analysis by combining wave equation based redatuming and kirchhoff based migration velocity analysis 审中-公开
    通过组合基于波动方程的回归和基于kirchhoff的移动速度分析的亚速度分析方法

    公开(公告)号：US20080106971A1

    公开(公告)日：2008-05-08

    申请号：US11879926

    申请日：2007-07-19

    Applicant: Bin Wang ,  Francois Audebert

    Inventor： Bin Wang ,  Francois Audebert

    IPC: G01V1/28 ,  G01V1/38

    CPC classification number: G01V1/303

    Abstract: A low-cost general method to perform subsalt velocity analysis is provided. For instances where sediment velocity structure is relatively simple, the method includes a single one-time redatuming to the base of salt, using existing prestack wave equation tools. For instances where the sediment velocity structure has a variable topography, the method includes multi-step redatuming to the base of salt. The method is designed to completely remove the salt-sediment overburden effects, and redatum the surface seismic data to a flat arbitrary subsalt datum, removing the complexity of the wavefield caused by the salt bodies. Once having obtained a simplified wavefield by stripping off the effects of the complex overburden, less expensive Kirchhoff imaging algorithms are employed for performing subsalt velocity model building.

    Abstract translation: 提供了一种执行子速度分析的低成本通用方法。 对于泥沙速度结构相对简单的情况，该方法包括使用现有的叠前波方程工具对盐基进行单次一次性重绘。 对于沉积物速度结构具有可变地形的情况，该方法包括多步地向盐的基底进行重新排列。 该方法旨在完全消除盐沉积物上覆层的影响，并将地表地震数据转换为平坦的任意盐点数据，消除盐体引起的波场复杂性。 一旦通过剥离复杂覆盖层的影响获得了简化的波场，则采用较便宜的基尔霍夫成像算法来执行亚速度模型建立。

    System and methods for retention-enhanced programmable shared gate logic circuit
    136.
    发明申请
    System and methods for retention-enhanced programmable shared gate logic circuit 审中-公开
    保持增强可编程共享门逻辑电路的系统和方法

    公开(公告)号：US20060226489A1

    公开(公告)日：2006-10-12

    申请号：US11095938

    申请日：2005-03-30

    Applicant: Bin Wang ,  Todd Humes

    Inventor： Bin Wang ,  Todd Humes

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/11521 ,  H01L27/11558

    Abstract: Retention-enhanced, programmable, shared floating gate logic circuits are employed as NVM cells. In one embodiment, the NVM cell is formed by a dual transistor logic gate circuit with a shared floating gate. The logic circuit is an inverter. The shared floating gate is doped partially or completely with p-type impurities to enhance retention. A charge adjustment circuit is arranged to inject and remove electrons to and from the shared floating gate determining the output of the logic gate circuit when supply voltage is applied to the logic gate circuit. In another embodiment, four transistors are employed to form another logic circuit such as a NOR gate or a NAND gate.

    Abstract translation: 采用保持增强型可编程共享浮栅逻辑电路作为NVM单元。 在一个实施例中，NVM单元由具有共享浮动栅极的双晶体管逻辑门电路形成。 逻辑电路是一个逆变器。 共享浮栅部分或完全掺杂有p型杂质以增强保留性。 电荷调整电路被布置成当向逻辑门电路施加电源电压时，向共享浮置栅极注入和去除电子，以确定逻辑门电路的输出。 在另一个实施例中，采用四个晶体管来形成诸如或非门或与非门的另一个逻辑电路。

    Inverter non-volatile memory cell and array system
    138.
    发明申请
    Inverter non-volatile memory cell and array system 有权
    逆变器非易失性存储单元和阵列系统

    公开(公告)号：US20060209598A1

    公开(公告)日：2006-09-21

    申请号：US11084214

    申请日：2005-03-17

    Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

    Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

    Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

    Increase of deposition rate of vapor deposited polymer by electric field
    140.
    发明授权
    Increase of deposition rate of vapor deposited polymer by electric field 失效
    通过电场提高气相沉积聚合物的沉积速率

    公开(公告)号：US6022595A

    公开(公告)日：2000-02-08

    申请号：US792044

    申请日：1997-01-31

    Applicant: John F. McDonald ,  Toh-Ming Lu ,  Bin Wang ,  Guang Rong Yang

    Inventor： John F. McDonald ,  Toh-Ming Lu ,  Bin Wang ,  Guang Rong Yang

    IPC: B05D1/00 ,  B05D7/24 ,  C23C16/44 ,  C08J7/06

    CPC classification number: B05D1/60 ,  C23C16/44 ,  B05D1/007

    Abstract: A method of depositing a polymer film onto a semiconductor wafer is provided which includes the steps of connecting the wafer to one terminal of a voltage source, connecting an electrode to an other pole of the voltage source and placing the electrode and substrate in superposed orientation to form a parallel plate capacitor, wherein an electric field is produced between the electrode and substrate. The parallel plate capacitor is placed in a chamber where pressure andc temperature are maintained at predetermined levels and gaseous monomers of the desired film to be polymerized are introduced into the chamber. The gaseous monomers are then permitted to flow between the electrode and wafer while the voltage of the electric field is maintained at a level sufficient to polarize the monomers without breaking their chemical bonds wherein the polarized monomers react to form a polymer film on the wafer at an enhanced rate.

    Abstract translation: 提供了一种在半导体晶片上沉积聚合物膜的方法，其包括以下步骤：将晶片连接到电压源的一个端子，将电极连接到电压源的另一个极，并将电极和衬底放置成叠置的方向 形成平行板电容器，其中在电极和基板之间产生电场。 将平行板电容器放置在压力和温度保持在预定水平的室中，并将待聚合的所需膜的气态单体引入室中。 然后允许气态单体在电极和晶片之间流动，同时电场的电压保持在足以使单体极化的水平，而不破坏其化学键，其中极化单体在晶片上反应形成聚合物膜， 增加率。

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