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190 条记录 (耗时 0.041 秒)

    Method of manufacturing a thin film transistor
    131.
    发明申请
    Method of manufacturing a thin film transistor 有权
    制造薄膜晶体管的方法

    公开(公告)号：US20070015318A1

    公开(公告)日：2007-01-18

    申请号：US11480929

    申请日：2006-07-06

    申请人： Yoshifumi Tanada ,  Kazuya Nakajima

    发明人： Yoshifumi Tanada ,  Kazuya Nakajima

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L27/1285 ,  H01L21/02532 ,  H01L21/02678 ,  H01L21/02683 ,  H01L21/02691 ,  H01L21/268 ,  H01L27/1218 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

    摘要： A method of manufacturing a semiconductor device characterized by its high-speed operation and high reliability is provided in which a semiconductor layer crystallized by a CW laser is used for an active layer of a TFT. When a semiconductor layer is crystallized by a CW laser, one part is formed of large crystal grains whereas another part is formed of microcrystals due to the width-wise energy density distribution. The former exhibits excellent electric characteristics. The latter has poor electric characteristics because grain boundaries hinder movement of electric charges, and therefore causes inconveniences when used as an active layer of a transistor. Accordingly, circuits are arranged such that a semiconductor layer formed of large crystal grains is used for the active layer of every TFT.

    摘要翻译： 提供一种制造半导体器件的方法，其特征在于其高速操作和高可靠性，其中通过CW激光器结晶的半导体层用于TFT的有源层。 当通过CW激光使半导体层结晶化时，由于晶体的宽度方向，所以一部分由大晶粒形成，另一部分由微晶构成。 前者表现出优异的电气特性。 后者由于晶界阻碍电荷的移动而具有差的电特性，因此当用作晶体管的有源层时会引起不便。 因此，电路被布置成使得由大晶粒形成的半导体层用于每个TFT的有源层。

    Semiconductor device and method for manufacturing the same
    133.
    发明授权
    Semiconductor device and method for manufacturing the same 失效

    公开(公告)号：US07078277B2

    公开(公告)日：2006-07-18

    申请号：US10996228

    申请日：2004-11-23

    申请人： Tatsuya Arao ,  Yoshifumi Tanada ,  Hiroshi Shibata

    发明人： Tatsuya Arao ,  Yoshifumi Tanada ,  Hiroshi Shibata

    IPC分类号： H01L21/00

    CPC分类号： G02F1/136213 ,  G02F1/136209 ,  G02F2201/40 ,  H01L27/1255 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645

    摘要： It is a problem to realize, by a reduced number of processes than that of the conventional, a reliable active-matrix liquid crystal display device having a high opening ratio for high-definition display. The present invention is characterized by: forming a gate electrode and source and drain interconnections in the same process, forming a first insulating film covering the interconnections, forming an upper light-shielding film on the first insulating film, forming a second insulating film on the upper light-shielding film, partially etching the first and second insulating films to form a contact hole reaching the drain interconnection, and forming a pixel electrode on the second insulating film to connect to the drain interconnection. Meanwhile, a holding capacitance is formed by the upper light-shielding film, the second insulating film and the pixel electrode.

    Semiconductor device
    134.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060061384A1

    公开(公告)日：2006-03-23

    申请号：US11270647

    申请日：2005-11-10

    申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

    发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

    IPC分类号： H03K19/0175

    CPC分类号： H01L29/786 ,  H03K19/01714 ,  H03K19/01721

    摘要： There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node α into a floating state. When the node α is in the floating state, a potential of the node α is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

    摘要翻译： 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点α成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅 - 源电容耦合，使得节点α的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。

    Display device and driving method thereof
    135.
    发明申请
    Display device and driving method thereof 有权
    显示装置及其驱动方法

    公开(公告)号：US20050219164A1

    公开(公告)日：2005-10-06

    申请号：US10885808

    申请日：2004-07-07

    申请人： Yoshifumi Tanada

    发明人： Yoshifumi Tanada

    IPC分类号： G09G3/30

    CPC分类号： G09G3/30 ,  G09G2300/0809 ,  G09G2320/0233

    摘要： In an active matrix display device, luminance distribution due to a voltage drop in a pixel portion is reduced, thereby obtaining a uniform display. In a display device having multiple current supply paths provided around the pixel portion, a current is supplied to the pixel portion using a current supply path selected among the multiple current supply paths, and the selected current supply path is switched with the passage of time to average the voltage distribution with time.

    摘要翻译： 在有源矩阵显示装置中，由于像素部分中的电压降引起的亮度分布减小，从而获得均匀的显示。 在具有设置在像素部周围的多个电流供给路径的显示装置中，使用从多个电流供给路径中选择的电流供给路径向像素部供给电流，并且将所选择的电流供给路径随时间切换到 平均随时间的电压分布。

    Pulse output circuit, shift register and electronic equipment
    139.
    发明授权
    Pulse output circuit, shift register and electronic equipment 有权
    脉冲输出电路，移位寄存器和电子设备

    公开(公告)号：US06813332B2

    公开(公告)日：2004-11-02

    申请号：US10756428

    申请日：2004-01-14

    申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    IPC分类号： G11C1900

    CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

    摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node &agr; is raised. When the potential of the node &agr; reaches (VDD−VthN), the node &agr; becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 On, while the potential of the node &agr; of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

    摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT105的阈值电压引起电压降。然后，后级的输出被输入到TFT 103，使TFT 103导通，而电位 的TFT102和106的节点α的下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。

    Pulse output circuit, shift register, and display device
    140.
    发明授权
    Pulse output circuit, shift register, and display device 有权

    公开(公告)号：US06646476B2

    公开(公告)日：2003-11-11

    申请号：US10145033

    申请日：2002-05-15

    申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

    发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

    IPC分类号： H01L21228

    摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.