公开(公告)号：US08026767B2

公开(公告)日：2011-09-27

申请号：US12545084

申请日：2009-08-21

Applicant: Chih-Wei Chen ,  Chuan-Jane Chao ,  Shyh-Chyi Wong

Inventor： Chih-Wei Chen ,  Chuan-Jane Chao ,  Shyh-Chyi Wong

IPC: H03F3/04

CPC classification number: H03F1/0266 ,  H03F1/56 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/108 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/555

Abstract: An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.

Abstract translation: 使用相对于功率电平提供更灵敏的自适应偏置电流的自适应偏置电路用于偏置电子电路。 自适应偏置电路具有耦合到电源的第一晶体管，耦合到第一晶体管的电压偏置电路和偏置第一晶体管的电源，以及耦合到第一晶体管和电子电路的第一功率耦合模块，用于耦合 输入信号功率的一部分到第一晶体管。 第二晶体管耦合到第一晶体管和电源以增加自适应偏置电路的电流增益，并且第二电流耦合模块耦合到第二晶体管和电子电路以向电子电路提供自适应偏置电流。

公开(公告)号：US07912172B2

公开(公告)日：2011-03-22

申请号：US12480106

申请日：2009-06-08

Applicant: Han-Hau Wu

Inventor： Han-Hau Wu

IPC: H03K21/00

CPC classification number: H03K23/667 ,  H03K23/68

Abstract: A programmable divider apparatus comprises a first divider, a second divider, a feedback control unit, and a plurality of control signals. The first divider provides a frequency division operation of division by at least three integers, the second divider is cascaded to the first divider to provide a frequency division operation of division by two integers. The feedback control unit is coupled to between the first divider and the second divider to provide a feedback control signal to selectively supply an output of the second divider to an input of the first divider. The apparatus control signals and the feedback control signal are used to execute the first divider or the second divider.

Abstract translation: 一种可编程分频装置包括第一分频器，第二分频器，反馈控制单元和多个控制信号。 第一分频器提供除以至少三个整数的分频运算，第二分频器级联到第一分频器以提供除以两个整数的分频运算。 反馈控制单元耦合到第一分压器和第二分压器之间以提供反馈控制信号，以选择性地将第二分频器的输出提供给第一分频器的输入。 装置控制信号和反馈控制信号用于执行第一分频器或第二分频器。

公开(公告)号：US20090055677A1

公开(公告)日：2009-02-26

申请号：US11892238

申请日：2007-08-21

Applicant: Tse-Peng Chen

Inventor： Tse-Peng Chen

IPC: G06F13/38 ,  G06F1/04

CPC classification number: G06F1/04 ,  G06F13/4059

Abstract: The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

Abstract translation: 本发明提供了异步先进先出（FIFO）接口和操作方法，其中异步FIFO接口的读出时钟和写入时钟是异步的。 异步FIFO接口包括FIFO缓冲器，时钟控制器和可变整数分频器。 FIFO缓冲器至少输入一个具有写入时钟的数据，并输出至少一个具有读出时钟的数据。 时钟控制器根据存储在FIFO缓冲器中的数据数量输出时钟控制信号。 可变整数分频器分割第一信号以通过由时钟控制信号控制的整数除数来产生读出时钟或写入时钟，以便调整存储在FIFO缓冲器中的数据的数量。

公开(公告)号：US07460851B2

公开(公告)日：2008-12-02

申请号：US11269729

申请日：2005-11-09

Applicant: Yu-Ling Chiu ,  Tsyr-Shyang Liou

Inventor： Yu-Ling Chiu ,  Tsyr-Shyang Liou

IPC: H04B1/28 ,  H04B1/46 ,  H01L21/00

CPC classification number: H04B1/38 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method and an apparatus for integrating a surface acoustic wave (SAW) filter and a transceiver are provided to solve the problem of having a large area of the prior-art integration of a SAW filter and a transceiver; wherein a device for integrating a SAW filter and a transceiver is provided and a component stack method is used to accomplish the integration of the SAW filter and the transceiver, and thus besides featuring a low cost and a small area as well as avoiding a signal loss, the invention can further include a design of encapsulating other components and chips, or even suitable to be used for various integrated circuit packaging technologies (such as QFP and BGA, etc.)

Abstract translation: 提供了一种用于集成表面声波（SAW）滤波器和收发器的方法和装置，以解决SAW滤波器和收发器的现有技术集成的大面积的问题; 提供了一种用于集成SAW滤波器和收发器的装置，并且使用组件堆叠方法来实现SAW滤波器和收发器的集成，因此除了具有低成本和小面积以及避免信号损失之外 本发明还可以包括封装其他部件和芯片的设计，或甚至适用于各种集成电路封装技术（例如QFP和BGA等）的设计，

公开(公告)号：US20080169883A1

公开(公告)日：2008-07-17

申请号：US11819281

申请日：2007-06-26

Applicant: Chia-Jen Hsu ,  Chuan-Jane Chao

Inventor： Chia-Jen Hsu ,  Chuan-Jane Chao

IPC: H03H7/00

CPC classification number: H03H5/00 ,  H01F17/0006 ,  H01F27/40

Abstract: An LC resonant circuit. The LC resonant circuit comprises an inductor and a conductor. The inductor is an electrode plate of a capacitor. The conductor is over, under, or on both sides of the inductor and used as the other electrode plate of the capacitor.

Abstract translation: LC谐振电路。 LC谐振电路包括电感器和导体。 电感器是电容器的电极板。 导体在电感器的两侧，下面或两侧，用作电容器的另一个电极板。

公开(公告)号：US07138880B2

公开(公告)日：2006-11-21

申请号：US11117321

申请日：2005-04-29

Applicant: Ssu-Pin Ma ,  Shao-Hua Chen

Inventor： Ssu-Pin Ma ,  Shao-Hua Chen

IPC: H03K3/02 ,  H03K3/26

CPC classification number: H03K3/013 ,  H03K3/012 ,  H03K3/0231

Abstract: A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while resuming a normal charging/discharging thereafter, and vice versa. The present invention makes use of the turbo-charging/discharging for a linear compensation, such that the produced oscillating signal has the features of concurrently eliminating phase noises and jitters as well as maintaining the modulation linearity.

Abstract translation: 一种用于产生振荡信号的方法包括：通过在充电之后放电到高触发电平并且在放电到低触发电平之后进行充电来产生振荡信号; 并且在从充电到放电的转换的初始阶段进行涡轮增压，同时在此之后恢复正常的充电/放电，反之亦然。 本发明利用用于线性补偿的涡轮增压/放电，使得所产生的振荡信号具有同时消除相位噪声和抖动以及维持调制线性的特征。

公开(公告)号：US20060105737A1

公开(公告)日：2006-05-18

申请号：US11269729

申请日：2005-11-09

Applicant: Yu-Ling Chiu ,  Tsyr-Shyang Liou

Inventor： Yu-Ling Chiu ,  Tsyr-Shyang Liou

IPC: H04B1/28

CPC classification number: H04B1/38 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method and an apparatus for integrating a surface acoustic wave (SAW) filter and a transceiver are provided to solve the problem of having a large area of the prior-art integration of a SAW filter and a transceiver; wherein a device for integrating a SAW filter and a transceiver is provided and a component stack method is used to accomplish the integration of the SAW filter and the transceiver, and thus besides featuring a low cost and a small area as well as avoiding a signal loss, the invention can further include a design of encapsulating other components and chips, or even suitable to be used for various integrated circuit packaging technologies (such as QFP and BGA, etc.)

Abstract translation: 提供了一种用于集成表面声波（SAW）滤波器和收发器的方法和装置，以解决SAW滤波器和收发器的现有技术集成的大面积的问题; 提供了一种用于集成SAW滤波器和收发器的装置，并且使用组件堆叠方法来实现SAW滤波器和收发器的集成，因此除了具有低成本和小面积以及避免信号损失之外 本发明还可以包括封装其他部件和芯片的设计，或甚至适用于各种集成电路封装技术（例如QFP和BGA等）的设计，

公开(公告)号：US20060103468A1

公开(公告)日：2006-05-18

申请号：US11124094

申请日：2005-05-09

Applicant: Jiong-Guang Su ,  Tsyr-Shyang Liou ,  Shyh-Chyi Wong

Inventor： Jiong-Guang Su ,  Tsyr-Shyang Liou ,  Shyh-Chyi Wong

IPC: H03F3/45

CPC classification number: H03F1/22 ,  H03F2200/294 ,  H03F2200/372

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract translation: 具有本发明的共源共栅拓扑的差分输出LNA的单端输入克服了现有技术的单端输入到差分输出LNA的电流和面积的更大的消耗。 LNA需要为每个晶体管提供工作偏置。 LNA具有几个晶体管，几个电容阻抗和几个电感阻抗。 本发明的主要目的不仅降低了成本并且节省了面积和电流消耗，而且与现有技术相比，在相同的电流消耗下也具有更高的线性度和增益。

公开(公告)号：US20250169194A1

公开(公告)日：2025-05-22

申请号：US18398178

申请日：2023-12-28

Applicant: RichWave Technology Corp.

Inventor： Ching-Yao Pai ,  Yu-Hung Chen

IPC: H01L27/02

Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit including a main transistor, a resistor element and a control circuit. A first voltage terminal is coupled to a second terminal of the main transistor and a first terminal of the resistor element. A second voltage terminal is coupled to a first terminal of the main transistor. The control circuit is coupled between a second terminal of the resistor element and a control terminal of the main transistor. When an ESD event occurs, the product of the capacitance value of a parasitic capacitance of the control circuit and the resistance value of the resistor element is greater than the duration of the ESD event, and the control circuit turns on the main transistor so that an ESD current flows through the main transistor.

公开(公告)号：US20250167542A1

公开(公告)日：2025-05-22

申请号：US18397960

申请日：2023-12-27

Applicant: RichWave Technology Corp.

Inventor： Ching-Yao Pai ,  Yu-Hung Chen

IPC: H02H9/04

Abstract: A transistor stack circuit including a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors, and a plurality of resistors is provided. The transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. A first terminal of each resistor is coupled to a common path. A second terminal of each resistor is coupled to a control terminal of a corresponding transistor among the transistors. The impedance unit is coupled between the common path and a reference voltage terminal. When an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each resistor, and the transistors form a low-impedance path.