公开(公告)号：US5216381A

公开(公告)日：1993-06-01

申请号：US808498

申请日：1991-12-17

Applicant: Edoardo Botti ,  Guido Brasca

Inventor： Edoardo Botti ,  Guido Brasca

IPC: H03F3/213 ,  H03F3/30 ,  H03F3/347 ,  H03F3/45

CPC classification number: H03F3/45286 ,  H03F3/3008 ,  H03F3/3037 ,  H03F3/45291 ,  H03F2203/45028 ,  H03F2203/45188 ,  H03F2203/45471

Abstract: Unitary-gain final stage particularly for monolithically integratable power amplifiers, which comprises a pair of final N-channel MOS power transistors. The first transistor has its drain terminal connected to a supply voltage and its source terminal connected to the drain terminal of the second transistor. The source terminal of the second transistor is connected to the ground. The output terminal of the power amplifier is connected between the source terminal of the first transistor and the drain terminal of the second transistor. The final stage furthermore comprises a high-gain feedback differential amplifier which has its non-inverting input terminal connected to the input of the power amplifier, its inverting input terminal connected to the output terminal of the differential amplifier and its output terminal connected to the gate terminal of the second transistor. A leveling circuit is furthermore connected to the gate terminal of the second transistor. A third MOS transistor has its source terminal connected to the input of the amplifier, and its gate terminal and drain terminal are connected to the gate terminal of the first transistor and to a first driven current source.

公开(公告)号：US5210481A

公开(公告)日：1993-05-11

申请号：US808484

申请日：1991-12-17

Applicant: Davide Brambilla ,  Edoardo Botti

Inventor： Davide Brambilla ,  Edoardo Botti

IPC: G05F1/56 ,  H03K17/041 ,  H03K17/082

CPC classification number: H03K17/04113 ,  H03K17/0826

Abstract: Voltage/current characteristics control circuit particularly for protecting power transistors, which comprises at least one power transistor; the emitter terminal of a first transistor is directly connected to the output of the power transistor; the emitter terminal of a second transistor is connected to the first terminal of the power transistor by means of a first resistor. The collector terminal and the base terminal of the first transistor are connected to a current source. The base terminal of the first transistor is connected to the base terminal of the second transistor, and the circuit furthermore comprises a protection circuitry. The circuitry is connected to the collector terminal of the second transistor through a differential stage which comprises a third transistor and a fourth transistor; the third transistor and fourth transistor have a respective second resistor and third resistor arranged in series. Divider means are furthermore provided and are interposed between the second terminal of the power transistor and the base terminals of the third transistor and fourth transistor.

公开(公告)号：US5204638A

公开(公告)日：1993-04-20

申请号：US808492

申请日：1991-12-17

Applicant: Davide Brambilla ,  Fabrizio Stefani

Inventor： Davide Brambilla ,  Fabrizio Stefani

IPC: H03F3/34 ,  H03F3/343 ,  H03F3/45

CPC classification number: H03F3/45479 ,  H03F3/3437

Abstract: Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor, by a second PNP transistor, by a third NPN transistor, by a fourth NPN transistor and by a first constant-current source, and a unitary-gain output stage. The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage, a gain stage which comprises a fifth NPN transistor which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor and to a seventh PNP transistor. The seventh transistor is connected to the sixth transistor. The seventh transistor and the sixth transistor are connected to the unitary-gain output stage.

公开(公告)号：US5187431A

公开(公告)日：1993-02-16

申请号：US716704

申请日：1991-06-18

Applicant: Giuseppe Libretti

Inventor： Giuseppe Libretti

IPC: G01R1/073 ,  G01R31/26 ,  H01L21/66 ,  H01R11/18 ,  H01R31/06

CPC classification number: H01R31/06 ,  G01R1/07378 ,  H01R12/52

Abstract: An universal connector employing a plurality of double female contacts installed with a certain clearance in receptacles of a body which may be suspended in a coupling position with a plurality of male contacts arranged on the top face of an EWS probe card and with a plurality of male contacts arranged on the bottom surface of a test card in a test-on-wafer station, provides a multicontact universal connection for any pair of so equipped cards of the inventories of probe cards and of test cards of the station. The connection is easily set up and exhibits excellent stability and uniformity characteristics of the electrical couplings, while reducing sensibly the time necessary for the setting-up and debugging of the test station for initiating a certain cycle of testing-on-wafer. The stability and reproducibility of the electrical couplings provided by the connection increases the precision of the measurements of critical parameters of the integrated devices with a positive effect on the production yield.

公开(公告)号：US5172018A

公开(公告)日：1992-12-15

申请号：US835654

申请日：1992-02-13

Applicant: Francesco Colandrea ,  Vanni Poletto

Inventor： Francesco Colandrea ,  Vanni Poletto

IPC: G05F1/56 ,  G05F1/575 ,  H03K17/082 ,  H03K17/16

CPC classification number: H03K17/0822 ,  G05F1/575 ,  H03K17/165

Abstract: Current control device particularly for power circuits in MOS technology, which comprises a MOSFET transistor which has its source terminal connected to one terminal of a dissipative load, its gate terminal connected to a pump circuit which receives in input a supply voltage and a square-waveform voltage, and its drain terminal connected to a power supply. The device furthermore comprises a control circuit which is coupled to the MOSFET transistor by means of an electrical connection and generates signals for adjusting the supply voltage and the square-waveform voltage of the pump circuit.

公开(公告)号：US5165066A

公开(公告)日：1992-11-17

申请号：US782894

申请日：1991-10-22

Applicant: Marco I. Buraschi

Inventor： Marco I. Buraschi

IPC: H01L21/8247 ,  G11C29/00 ,  G11C29/12 ,  H01L21/3205 ,  H01L21/66 ,  H01L21/822 ,  H01L23/485 ,  H01L23/52 ,  H01L23/544 ,  H01L27/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L22/34 ,  H01L23/485 ,  H01L2924/0002

Abstract: A contact chain structure, for troubleshooting integrated circuits of EPROM memories, of a type comprising cluster contacts connecting metallization layers to active areas of the circuit, comprises a source-drain region implanted centrally of each active area. Deposited over that region is a gate region which, on being biased, enables the conductive condition of the chain to be varied.

公开(公告)号：US5142204A

公开(公告)日：1992-08-25

申请号：US713691

申请日：1991-06-11

Applicant: Silvano Gornati ,  Mauro Merlo ,  Maurizio Zuffada ,  Loic Lietar

Inventor： Silvano Gornati ,  Mauro Merlo ,  Maurizio Zuffada ,  Loic Lietar

IPC: G09G1/04 ,  G09G1/12 ,  G09G1/16 ,  H04N3/27 ,  H04N5/46

CPC classification number: G09G1/167 ,  G09G1/04 ,  G09G1/16

Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit incorporating,a frequency meter being input and analog synchronization signal.a phase comparator having two inputs and in turn receiving said synchronization signal on one input,a voltage-controlled oscillator adapted to output a signal whose frequency is depending on said voltage and operatively linked to an output of said phase comparator, anda counter connected with its input, on the one side, to the oscillator output, and on the other side, to the meter output, said counter having an output connected to the other input of the phase comparator also forming the integrated circuit output.

公开(公告)号：US5140542A

公开(公告)日：1992-08-18

申请号：US531719

申请日：1990-06-01

Applicant: Michele Taliercio ,  Mario Lavorgna ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

Inventor： Michele Taliercio ,  Mario Lavorgna ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

IPC: G06F17/14 ,  G06F17/16

CPC classification number: G06F17/14 ,  G06F17/16

Abstract: A method for the arithmetical calculation of two-dimensional transforms including two time steps of multiplication and accumulation, of which the first step is assigned to the product of the data and of the coefficient matrices and the second step is assigned to the subsequent product by the transposed coefficient matrix. Moreover, preferably the data to be transformed and the corresponding coefficients are supplied to a first multiplication step in time succession, possibly after their storage in an appropriate memory. The device for the attainment of the method includes two multipliers with their corresponding accumulator, a random-access type memory for storing the data to be transformed and the transform coefficients, a multiplexer which receives the data first from the input and then from the memory and arranges them in a time succession for the supply to a first multiplier, and a shift register which receives the transform coefficients from the memory and arranges them for the supply to the second multiplier.

公开(公告)号：US5140515A

公开(公告)日：1992-08-18

申请号：US498268

申请日：1990-03-23

Applicant: Pietro Menniti ,  Antonella Baiocchi

Inventor： Pietro Menniti ,  Antonella Baiocchi

IPC: G05F1/10 ,  H02P7/00 ,  H02P8/12

CPC classification number: H02P8/12 ,  H02P7/04

Abstract: An electronic circuit for measuring and controlling an electric current flowing through an inductive electric load, being of a type which comprises a first, field-effect power transistor connected to the load and a second, sensing transistor having its source electrode connected to the source electrode of the first transistor, further comprises a voltage comparator having respective inputs connected to the corresponding drain electrodes of said transistors, and an electronic switch connected in ahead of the gate electrode of the power transistor and linked to the comparator output.

公开(公告)号：US5134481A

公开(公告)日：1992-07-28

申请号：US631915

申请日：1990-12-21

Applicant: Silvano Gornati ,  Giorgio Betti ,  Fabrizio Sacchi ,  Gianfranco Vai ,  Maurizio Zuffada

Inventor： Silvano Gornati ,  Giorgio Betti ,  Fabrizio Sacchi ,  Gianfranco Vai ,  Maurizio Zuffada

IPC: G01R23/10 ,  H04N5/04 ,  H04N5/46 ,  H04N17/00

CPC classification number: H04N17/00 ,  H04N5/04 ,  H04N5/46

Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.