公开(公告)号：US07939856B2

公开(公告)日：2011-05-10

申请号：US11325236

申请日：2006-01-03

Applicant: Joshipura Jwalant ,  Nitin Bansal ,  Amit Katyal ,  Massimiliano Picca

Inventor： Joshipura Jwalant ,  Nitin Bansal ,  Amit Katyal ,  Massimiliano Picca

IPC: H01L27/118 ,  H01L29/66

CPC classification number: H05K3/30 ,  G06F17/5063 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract translation: 一种用于集成电压调节器的区域有效的分布式装置，其包括连接在芯片的I / O轨上的一对PADS与至少一个具有所述装置的小尺寸复制品的附加填充单元之间的填充单元耦合到所述I / O 用于在所述芯片的外围分配所述设备的副本的轨道。 该装置作为小尺寸复制品连接在所述第二填充单元的下部，用于在所述芯片的周围分配所述装置并提供最大的面积利用率。

公开(公告)号：US20110102062A1

公开(公告)日：2011-05-05

申请号：US12732604

申请日：2010-03-26

Applicant: H.C. PRAVEENA

Inventor： H.C. PRAVEENA

IPC: G05F1/00

CPC classification number: H03K19/00369

Abstract: Systems and methods for achieving multiple supply voltage compatibility of an input/output (I/O) ring of an integrated circuit (IC) chip. The IC chip includes a core surrounded by the I/O ring which includes a voltage detector circuit. An I/O supply voltage of the IC chip is sensed by the voltage detector circuit to generate a control signal. The control signal is used to configure the I/O ring to operate at the I/O supply voltage of the I/O ring, thus enabling the IC to operate at multiple supply voltage levels.

Abstract translation: 用于实现集成电路（IC）芯片的输入/输出（I / O）环的多电源电压兼容性的系统和方法。 IC芯片包括由包括电压检测器电路的I / O环包围的芯。 IC芯片的I / O电源电压由电压检测器电路感测以产生控制信号。 控制信号用于将I / O环配置为在I / O环的I / O电源电压下工作，从而使IC能够以多个电源电压工作。

公开(公告)号：US20110062983A1

公开(公告)日：2011-03-17

申请号：US12650092

申请日：2009-12-30

Applicant: Nitin Gupta ,  Tapas Nandy ,  Phalguni Bala ,  Pikul Sarkar

Inventor： Nitin Gupta ,  Tapas Nandy ,  Phalguni Bala ,  Pikul Sarkar

IPC: H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361 ,  H03K19/018514

Abstract: Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems.

Abstract translation: 这里描述了用于操作发射机电路以减少影响正在产生的信号的噪声并减少抖动的各种原理。 在一些实施例中，以使得至少一个开关至少对于每一位进行改变状态的切换发生在等于或高于传输比特率的方式来操作电路。 以这种方式操作电路导致高于电路的谐振频率的开关速率，并且防止大的振荡和噪声被插入到信号中并导致通信问题。

公开(公告)号：US20110001458A1

公开(公告)日：2011-01-06

申请号：US12698328

申请日：2010-02-02

Applicant: Nitin Bansal ,  Kallol Chatterjee

Inventor： Nitin Bansal ,  Kallol Chatterjee

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.

Abstract translation: 这里描述的是用于设计和操作电压调节器的原理，其将稳定且准确地运行，而无需外部电容用于所有或宽范围的负载电路和负载电路的特性。 根据这些原理中的一些，公开了一种电压调节器，其具有多个反馈回路，每个响应于不同速度的瞬变，其并联操作以响应于由于输出电流/电压的变化而调节调节器的输出电流 ，例如，电源电压的变化和/或负载电流的变化。 以这种方式，电压调节器可以快速响应输出电流/电压的变化，并且可以避免进入不稳定状态。

公开(公告)号：US07856467B2

公开(公告)日：2010-12-21

申请号：US11324019

申请日：2005-12-29

Applicant: Parvesh Swami ,  Ankur Bal

Inventor： Parvesh Swami ,  Ankur Bal

IPC: G06F7/52

CPC classification number: G06F7/523 ,  G06F7/5312

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract translation: 本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。

公开(公告)号：US07852159B2

公开(公告)日：2010-12-14

申请号：US12178769

申请日：2008-07-24

Applicant: Pratap Narayan Singh ,  Chandrajit Debnath

Inventor： Pratap Narayan Singh ,  Chandrajit Debnath

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F2200/453 ,  H03F2203/45292 ,  H03F2203/45356 ,  H03F2203/45626 ,  H03F2203/45682

Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

Abstract translation: 自适应偏置技术可以完全提高差分增益提升运算放大器的瞬态特性并降低功耗。 自适应偏置模块包括偏置生成模块和偏置复制模块。 偏置产生模块产生第一控制信号（VCMNB），并且将第一控制信号作为差分增强器的输出共模（偏置复制模块内部）施加。 偏置复制模块耦合到偏置产生模块，用于利用第一控制信号（VCMNB）对差分升压器的共模进行均衡。

公开(公告)号：US07814385B2

公开(公告)日：2010-10-12

申请号：US11848107

申请日：2007-08-30

Applicant: Swapnil Bahl

Inventor： Swapnil Bahl

IPC: G01R31/28

CPC classification number: G11C29/16 ,  G06F11/27 ,  G11C2029/0401

Abstract: A built-in self-test (BIST) device tests multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a memory test algorithm. The delay generator provides a delay of an expected data, a valid signal, a BBAD signal, a BEND signal, and a BFAIL signal. The multiple interface modules provide signal pipelining for multiple memories through a bus. The bus carries signals form the BIST device to multiple memories and vice-versa. The memory wrapper decodes a selected memory for decompressing a memory data signal generated by said BIST device and further compresses a memory output signal.

Abstract translation: 内置的自检（BIST）设备可以测试不同特性的多个嵌入式存储器。 BIST包括一个BIST控制器，一个延迟发生器，多个接口模块和一个内存包装器。 BIST控制器生成初始化序列和存储器测试算法。 延迟发生器提供期望数据，有效信号，BBAD信号，BEND信号和BFAIL信号的延迟。 多个接口模块通过总线为多个存储器提供信号流水线。 总线将信号从BIST设备传送到多个存储器，反之亦然。 存储器包装器对所选择的存储器进行解码，以解压缩由所述BIST设备生成的存储器数据信号，并进一步压缩存储器输出信号。

公开(公告)号：US07791970B2

公开(公告)日：2010-09-07

申请号：US11856801

申请日：2007-09-18

Applicant: Tanmoy Roy ,  Nasim Ahmad

Inventor： Tanmoy Roy ,  Nasim Ahmad

IPC: G11C7/10

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C16/26

Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Abstract translation: 电路包括第一预充电模块，第一多路复用器模块，第二预充电模块，第二多路复用器模块，读出放大器电路，第三预充电模块，输出模块。 电路可操作地耦合到第一核心块和第二核心块以提供期望的匹配特征。 第一核心块和第二核心块是用于存储用于读写操作的数据位的存储器块。 该电路利用与核心块之一的独特操作耦合来提供匹配特性。

公开(公告)号：US20100207957A1

公开(公告)日：2010-08-19

申请号：US12388420

申请日：2009-02-18

Applicant: Salil Taneja ,  Gaurav Jairath ,  Sachin Gupta ,  Rohit Kumar Jain

Inventor： Salil Taneja ,  Gaurav Jairath ,  Sachin Gupta ,  Rohit Kumar Jain

IPC: G09G5/02 ,  G09G5/00

CPC classification number: G09G5/397 ,  G09G5/393 ,  G09G2340/125 ,  G09G2370/20

Abstract: The embodiments of the present disclosure teach overlaying videos on a display device. The technique involves one or more buffers at input such as a first buffer (Primary Buffer) and an overlay buffer, a blitting module, a second buffer(Frame Buffer), and a display screen. The first buffer provides a first image data to the blitting module and the overlay buffer provides a second image data to the blitting module. The embodiments of the present disclosure demonstrate overlaying the second image on the first image with enhanced configurable functionality (like stretching, clipping, color keying, Alpha Blending and Raster Operation) if required, without modifying the Primary Buffer without the need of any overlay support in hardware.

Abstract translation: 本公开的实施例教导了在显示设备上重叠视频。 该技术涉及输入处的一个或多个缓冲器，例如第一缓冲器（主缓冲器）和覆盖缓冲器，触发模块，第二缓冲器（帧缓冲器）和显示屏。 第一个缓冲器向划线模块提供第一图像数据，并且覆盖缓冲器向划线模块提供第二图像数据。 本公开的实施例示出了如果需要，增强的可配置功能（例如拉伸，剪切，颜色键控，Alpha混合和栅格操作）在第一图像上覆盖第二图像，而不需要修改主缓冲器，而不需要任何覆盖支持 硬件。

公开(公告)号：US20100165755A1

公开(公告)日：2010-07-01

申请号：US12345959

申请日：2008-12-30

Applicant: Kedar Janardhan Dhori

Inventor： Kedar Janardhan Dhori

IPC: G11C7/00 ,  G11C11/416

CPC classification number: G11C7/14 ,  G11C7/08 ,  G11C16/28

Abstract: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.

Abstract translation: 基于单端位线的存储系统。 存储系统包括第一组存储单元，第二组存储单元，第一组参考存储单元，第二组参考存储单元和差分感测块。 存储核心垂直分成两半，以形成第一组存储单元和第二组存储单元。 第一组参考存储单元提供比用于存储数据的所述第一组和第二组存储单元的放电速率低的放电率。 第二组参考存储单元提供比用于存储数据的所述第一组和第二组存储单元的放电速率低的放电速率。 差分感测块耦合到第一组存储单元和第二组存储单元，用于在接收控制信号时产生输出数据信号。