公开(公告)号：US08576102B2

公开(公告)日：2013-11-05

申请号：US13310932

申请日：2011-12-05

Applicant: Chandrajit Debnath ,  Pratap Narayan Singh

Inventor： Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/10

CPC classification number: H03M1/1038 ,  H03M1/46

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract translation: 对模拟输入信号进行采样，并将采样的模拟输入信号转换为数字值。 还对采样的校准值进行采样，并根据采样的校准值计算N位偏移值的单个位。 替代地执行采样操作，使得针对每个产生的数字值产生偏移值的一个位。 例如，该过程重复N次以计算偏移值的所有N位，同时生成N个数字值。

公开(公告)号：US07852159B2

公开(公告)日：2010-12-14

申请号：US12178769

申请日：2008-07-24

Applicant: Pratap Narayan Singh ,  Chandrajit Debnath

Inventor： Pratap Narayan Singh ,  Chandrajit Debnath

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F2200/453 ,  H03F2203/45292 ,  H03F2203/45356 ,  H03F2203/45626 ,  H03F2203/45682

Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

Abstract translation: 自适应偏置技术可以完全提高差分增益提升运算放大器的瞬态特性并降低功耗。 自适应偏置模块包括偏置生成模块和偏置复制模块。 偏置产生模块产生第一控制信号（VCMNB），并且将第一控制信号作为差分增强器的输出共模（偏置复制模块内部）施加。 偏置复制模块耦合到偏置产生模块，用于利用第一控制信号（VCMNB）对差分升压器的共模进行均衡。

公开(公告)号：US20090027126A1

公开(公告)日：2009-01-29

申请号：US12178769

申请日：2008-07-24

Applicant: Pratap Narayan Singh ,  Chandrajit Debnath

Inventor： Pratap Narayan Singh ,  Chandrajit Debnath

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F2200/453 ,  H03F2203/45292 ,  H03F2203/45356 ,  H03F2203/45626 ,  H03F2203/45682

Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

Abstract translation: 自适应偏置技术可以完全提高差分增益提升运算放大器的瞬态特性并降低功耗。 自适应偏置模块包括偏置生成模块和偏置复制模块。 偏置产生模块产生第一控制信号（VCMNB），并且将第一控制信号作为差分增强器的输出共模（偏置复制模块内部）施加。 偏置复制模块耦合到偏置产生模块，用于利用第一控制信号（VCMNB）对差分升压器的共模进行均衡。

公开(公告)号：US08421519B2

公开(公告)日：2013-04-16

申请号：US12615991

申请日：2009-11-10

Applicant: Chandrajit Debnath ,  Anubhuti Rangbulla

Inventor： Chandrajit Debnath ,  Anubhuti Rangbulla

IPC: H03K5/00

CPC classification number: G06G7/18

Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract translation: 一种在连续或离散时间电路中的开关电荷存储元件积分器，所述积分器包括差分输入放大器，第一2端电荷存储元件，第二二端电荷存储元件和多个受控开关。 差分输入放大器耦合到电容器和电阻器，并被配置为反相积分器。 放大器的反相端子耦合到两个受控开关。 放大器的非反相端子耦合到参考电压。 第一和第二开关电荷存储元件块分别在第二时钟信号和第一时钟信号的有效状态下交替耦合到放大器XOPA的反相端INM，以使供电噪声连续并且消除其对 时钟相位，从而使其与时钟信号的卷积归零。

公开(公告)号：US07671676B2

公开(公告)日：2010-03-02

申请号：US11900928

申请日：2007-09-12

Applicant: Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik

Inventor： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik

IPC: H03F3/45

CPC classification number: H03F3/45659 ,  H03F1/3211 ,  H03F3/45183 ,  H03F2203/45404 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45434 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

Abstract: A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

Abstract translation: 连续时间共模反馈模块能够在宽范围的输入电压下工作。 共模反馈模块包括共模检测器和用于计算和放大第一输入信号和第二输入信号的参考电压和共模电压的差的放大器。 共模反馈模块包括共模分解器和彼此耦合以提供共模反馈电压的控制电压产生模块。 共模反馈模块提供良好的线性度和宽带宽，无需补偿要求。 共模反馈模块还提供偏置电流和共模偏移的小过程角依赖性。

公开(公告)号：US20080068083A1

公开(公告)日：2008-03-20

申请号：US11900929

申请日：2007-09-12

Applicant: Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Sharma

Inventor： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Sharma

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H03F3/45192 ,  H03F3/45659 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

Abstract: Embodiments of the present invention provide a low voltage continuous time common mode feedback (CMFB) module, for low voltage operational amplifiers, providing good linearity, wide bandwidth and low systematic offset. The common mode feedback module includes a controlling module and an initializing module. The controlling module and the initializing module are parallel common mode feedback loops. The controlling module is a main CMFB loop and the initializing module is an auxiliary CMFB loop and both the loops work simultaneously. The controlling module and the initializing module receive a first differential input voltage and a second differential input voltage supplied by differential outputs of a main differential amplifier. Both the CMFB loops are low gain amplifiers in order to provide operation as linear as possible over the entire differential output operating range of the main differential amplifier.

Abstract translation: 本发明的实施例为低电压运算放大器提供低电压连续时间共模反馈（CMFB）模块，提供良好的线性度，宽带宽和低系统偏移。 共模反馈模块包括控制模块和初始化模块。 控制模块和初始化模块是并联共模反馈回路。 控制模块是主CMFB循环，初始化模块是辅助CMFB循环，两个循环同时工作。 控制模块和初始化模块接收由主差分放大器的差分输出提供的第一差分输入电压和第二差分输入电压。 CMFB环路都是低增益放大器，以便在主差分放大器的整个差分输出工作范围内提供尽可能线性的操作。

公开(公告)号：US08766697B2

公开(公告)日：2014-07-01

申请号：US13563869

申请日：2012-08-01

Applicant: Adeel Ahmad ,  Chandrajit Debnath

Inventor： Adeel Ahmad ,  Chandrajit Debnath

IPC: H03L5/00

CPC classification number: H03L5/00 ,  H03F3/45179 ,  H03K19/018528

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract translation: 放大器具有耦合在电压供应节点和输出节点之间的第一上拉通路，以及耦合在输出节点和地电源节点之间的下拉通路。 第二上拉路径耦合在电压供应节点和输出节点之间。 第二上拉路径由反馈信号驱动并被偏置信号偏置。 反相器电路可操作以反转放大器输出节点处的信号以产生反馈信号。 偏置电路被配置为产生偏置信号。 偏置电路被配置为控制到第二上拉路径的下拉路径的相对强度，其中下拉路径以一致地存在于所有PVT角上的方式比第二上拉路径更强 。

公开(公告)号：US20110001518A1

公开(公告)日：2011-01-06

申请号：US12650041

申请日：2009-12-30

Applicant: Chandrajit Debnath ,  Vigyan Jain ,  Adeel Ahmad

Inventor： Chandrajit Debnath ,  Vigyan Jain ,  Adeel Ahmad

IPC: H03K17/00

CPC classification number: G11C27/024 ,  G11C27/026

Abstract: Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal.

Abstract translation: 用于操作开关电容器电路以减少输入和反馈依赖性和/或减少参考调制的技术。 开关电容电路可以分四个阶段工作。 在一个周期开始的第一阶段，通过共模信号对电容器进行充电/放电，以从前一个周期屏蔽存储在电容器中的剩余电荷。 在第二阶段，电容器用输入信号充电。 在第三阶段期间，电容器被带宽宽带辅助参考信号，而在第四阶段期间，电容器用参考信号充电。 在第三和第四阶段期间，电容器可以耦合到积分电路以整合输入信号和参考信号之间的差异。

公开(公告)号：US08120385B2

公开(公告)日：2012-02-21

申请号：US12512824

申请日：2009-07-30

Applicant: Pratap Singh ,  Chandrajit Debnath

Inventor： Pratap Singh ,  Chandrajit Debnath

IPC: G01R19/00

CPC classification number: H03K3/356139 ,  H03K3/013

Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Abstract translation: 本公开涉及通过借助于具有与输入差分对的属性类似的电压控制开关实现的电荷注入来减少比较器中反冲的影响。 电压控制开关产生电荷以中和比较器中的输入锁存期间的电荷损失。

公开(公告)号：US07737780B2

公开(公告)日：2010-06-15

申请号：US11900917

申请日：2007-09-12

Applicant: Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Arnold James D'Souza

Inventor： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Arnold James D'Souza

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F3/45677 ,  H03F2203/45052 ,  H03F2203/45074 ,  H03F2203/45248 ,  H03F2203/45296 ,  H03F2203/45302 ,  H03F2203/45318 ,  H03F2203/45342 ,  H03F2203/45356

Abstract: Embodiments of the present invention disclose operational amplifiers which demonstrate good settling behavior with minimum over-shoot or ringing for improving settling behavior. The amplifiers include one or more amplification stages connected to form a symmetric structure. The amplification stage includes a boosting amplifier, a MOS transistor and a compensation capacitor. The MOS transistor can be an NMOS transistor and a PMOS transistor. Using this scheme pole-zero doublets are rearranged in a manner to improve the transient settling response.

Abstract translation: 本发明的实施例公开了运行放大器，其以最小的过冲或振铃来表现出良好的沉降行为，以改善沉降行为。 放大器包括一个或多个连接以形成对称结构的放大级。 放大级包括升压放大器，MOS晶体管和补偿电容器。 MOS晶体管可以是NMOS晶体管和PMOS晶体管。 使用该方案，极点双重重排以改善瞬态稳定响应的方式。