公开(公告)号：USRE41561E1

公开(公告)日：2010-08-24

申请号：US12110205

申请日：2008-04-25

申请人： Ankur Bal

发明人： Ankur Bal

IPC分类号： H01L25/00

CPC分类号： H03K19/17728

摘要： A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

摘要翻译： 提供了一种用于减少实现布尔函数所需的查找表中可编程体系结构元素数量或相同或逻辑等价的操作的系统。 该系统可以包括连接到多个解码器的输入的单组存储元件，并且存储元件可以由解码器同时访问以向其提供同时多个输出。

公开(公告)号：US07180792B2

公开(公告)日：2007-02-20

申请号：US10377297

申请日：2003-02-28

申请人： Ankur Bal ,  Manish Agarwal

发明人： Ankur Bal ,  Manish Agarwal

IPC分类号： G11C7/10

CPC分类号： H03K19/17776 ,  G11C7/20 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

摘要： An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device includes a group of one or more data latches, each including a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring significant additional circuitry.

摘要翻译： 一种用于在包括FPGA和存储器件的电子设备中初始化锁存器阵列的有效方法和电子电路包括一组一个或多个数据锁存器，每个数据锁存器包括一对交叉耦合的反相逻辑元件，其特征在于，它包括一个装置 用于同时将每个数据锁存器初始化为预定的逻辑状态，而不需要显着的附加电路。

公开(公告)号：US07030648B2

公开(公告)日：2006-04-18

申请号：US10739395

申请日：2003-12-18

申请人： Ankur Bal ,  Namerita Khanna

发明人： Ankur Bal ,  Namerita Khanna

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

摘要翻译： 本发明涉及一种高性能互连架构，其提供减少的延迟最小化的电迁移和FPGA中的减少的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块由互连段链接，该互连段通过互连层在中间逻辑块上以直线路由，并且通过连接段选择性地连接到每端的逻辑块。

公开(公告)号：US09225321B2

公开(公告)日：2015-12-29

申请号：US13172647

申请日：2011-06-29

申请人： Ankur Bal ,  Anupam Jain

发明人： Ankur Bal ,  Anupam Jain

IPC分类号： G06F1/12 ,  G06F1/00 ,  H03K5/135 ,  H04L7/02

CPC分类号： H03K5/135 ,  G06F1/12 ,  H04L7/0045 ,  H04L7/02

摘要： Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.

摘要翻译： 公开了信号同步系统和方法。 信号同步系统包括顺序逻辑电路，用于接收输入信号并根据时钟信号从输入信号产生多个中间信号。 逻辑电路组合中间信号以产生输出信号。 信号接收机包括耦合到微控制器的微控制器和信号同步器。 信号同步器包括顺序逻辑电路，用于接收来自发射机的输入信号，并且基于时钟信号从所接收的输入信号产生多个中间信号。 逻辑电路组合中间信号以产生输出信号。

公开(公告)号：US20110279292A1

公开(公告)日：2011-11-17

申请号：US12842311

申请日：2010-07-23

申请人： Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

发明人： Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

IPC分类号： H03M7/12 ,  H03M1/66

CPC分类号： H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

摘要： A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

摘要翻译： 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

公开(公告)号：US20110142254A1

公开(公告)日：2011-06-16

申请号：US12766210

申请日：2010-04-23

申请人： Ankur BAL ,  Anupam Jain ,  Rakhel Kumar Parida

发明人： Ankur BAL ,  Anupam Jain ,  Rakhel Kumar Parida

IPC分类号： H04B15/00

CPC分类号： G10K11/002 ,  G10L21/0208 ,  G10L21/0232 ,  H04L5/0008 ,  H04L25/03159 ,  H04L27/2649 ,  H04L2025/03414

摘要： A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.

摘要翻译： 用于噪声去除的系统耦合到提供数字信号的信号单元。 噪声去除系统包括：将数字信号变换为f数字信号的变换模块，基于阈值分布的f数字信号产生无噪声信号的阈值滤波器;以及信号合成器，用于向 并将无噪声信号变换为输出信号。

公开(公告)号：US06646465B2

公开(公告)日：2003-11-11

申请号：US10072461

申请日：2002-02-07

申请人： Ankur Bal

发明人： Ankur Bal

IPC分类号： G11C1900

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

公开(公告)号：US08738679B2

公开(公告)日：2014-05-27

申请号：US12565596

申请日：2009-09-23

申请人： Rakhel Kumar Parida ,  Ankur Bal ,  Anupam Jain

发明人： Rakhel Kumar Parida ,  Ankur Bal ,  Anupam Jain

IPC分类号： G06F17/17 ,  H03H17/06

CPC分类号： H03H17/0664 ,  H03H17/0282 ,  H03H17/0657 ,  H03H17/0671

摘要： An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.

摘要翻译： 无偏移的正弦内插滤波器包括以第一采样频率工作的微分器，以第二采样频率工作的积分器和一个或多个系数乘法器。 系数乘法器将接收到的值与常数系数值相乘以产生输出值。 微分器，积分器和系数乘法器可以直接地或通过其他部件（例如加法器和延迟元件）或两者的组合来可操作地耦合。 在操作中，输入信号以第一采样频率提供给正弦内插滤波器。 输入信号由微分器，积分器和系数乘法器处理，以产生第二采样频率的输出信号。 产生输出信号后，积分器在下一个输入周期开始之前被复位。

公开(公告)号：US08645445B2

公开(公告)日：2014-02-04

申请号：US12614004

申请日：2009-11-06

申请人： Ankur Bal ,  Anupam Jain

发明人： Ankur Bal ,  Anupam Jain

IPC分类号： G06F17/17

CPC分类号： H03H17/0286 ,  H03H17/0671

摘要： The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.

摘要翻译： 本发明可以提供一种用于在信号的频率响应中补偿下降的方法和滤波器块。 滤波器块可以包括抽取器，其将高频输入信号抽取到设定频率输出信号。 设定频率可以是例如输入信号的奈奎斯特频率。 此外，滤波器块可以包括下降补偿器，其补偿来自抽取器的输出信号的频率响应中的下降。 下降补偿器可以使用递归滤波器制造，而不是大抽头FIR滤波器，这可能导致较少的存储器消耗和降低的功耗。

公开(公告)号：US20130110898A1

公开(公告)日：2013-05-02

申请号：US13468924

申请日：2012-05-10

申请人： Ankur BAL ,  Anupam JAIN ,  Neha BHARGAVA

发明人： Ankur BAL ,  Anupam JAIN ,  Neha BHARGAVA

IPC分类号： G06F17/10

CPC分类号： H03H17/0664

摘要： A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

摘要翻译： 信号处理器包括一个或多个存储体，其中每个存储体存储滤波器系数; 和一个或多个系数多路复用器单元; 每个系数多路复用器单元与存储器组相关联，并且基于所接收的输入采样的数量来检索滤波器系数。 处理器包括一个或多个乘法和累积（MAC）单元，每个MAC单元与系数多路复用器单元相关联，并且确定所检索的滤波器系数与输入采样的乘积; 检索存储在相关联寄存器中的先前值; 计算以前的值和乘积的总和; 并将求和存储在相关联的寄存器中。 处理器包括输出多路复用器单元，用于选择寄存器，并将存储在寄存器中的值提供为输出。