公开(公告)号：US20050274990A1

公开(公告)日：2005-12-15

申请号：US10820320

申请日：2004-06-08

Applicant: Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/768 ,  H03K5/08

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

公开(公告)号：US06960811B2

公开(公告)日：2005-11-01

申请号：US10929735

申请日：2004-08-30

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0266

Abstract: A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

Abstract translation: 低电容ESD保护器件。 该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱 以及所述第一和第二晶体管以及所述阱中的所述第二导电类型的掺杂区域，其中所述第一和第二晶体管中的每一个的漏极和源极区域的轮廓是不对称的，并且所述漏极区域的面积为 小于第一和第二晶体管中的每一个中的源极区域。

公开(公告)号：US20050180071A1

公开(公告)日：2005-08-18

申请号：US10779341

申请日：2004-02-13

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongehen Ong

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongehen Ong

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0266 ,  H01L27/0288

Abstract: A circuit and a method for ESD protection are disclosed. The circuit includes an ESD protection circuit coupled to a pad. A device is coupled to the pad and an internal circuit. The device generates a voltage drop between the pad and the internal circuit, protecting thin oxide layers of the internal circuit from damage. The method comprises coupling an internal circuit to an ESD protection circuit and generating a voltage drop between a pad and the internal circuit to protect thin oxide layers of the internal circuit from damage when an ESD pulse is coupled to the pad.

Abstract translation: 公开了一种用于ESD保护的电路和方法。 电路包括耦合到焊盘的ESD保护电路。 器件耦合到焊盘和内部电路。 该器件在焊盘和内部电路之间产生电压降，保护内部电路的薄氧化物层免受损坏。 该方法包括将内部电路耦合到ESD保护电路并且在衬垫和内部电路之间产生电压降，以在ESD脉冲耦合到衬垫时保护内部电路的薄氧化物层免受损坏。

公开(公告)号：US20050176195A1

公开(公告)日：2005-08-11

申请号：US11072014

申请日：2005-03-04

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC classification number: H01L27/0251

Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

公开(公告)号：US20050041346A1

公开(公告)日：2005-02-24

申请号：US10644718

申请日：2003-08-20

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0285

Abstract: A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.

Abstract translation: 用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。 传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。 该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

公开(公告)号：US06747857B1

公开(公告)日：2004-06-08

申请号：US10062706

申请日：2002-02-01

Applicant: Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

IPC: H02H900

CPC classification number: H03K17/0822 ,  H01L27/0266 ,  H03K17/6872

Abstract: A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.

Abstract translation: 对于用于互补级联的NMOS输出电路串的ESD保护器件描述了一种新颖的器件和工艺。 本发明包括一个钳位NMOS，其栅极通过二极管连接到输入或输出焊盘，并通过电阻器连接到地。 钳位装置漏极连接到有源输出NMOS的信号栅极，钳位装置源连接到地。 ESD事件导致二极管进入击穿模式，并且电阻两端的导通电流在夹紧装置门上施加正电压，使夹紧装置打开。 这将有源NMOS信号栅极钳位到地，确保在ESD事件期间输出NMOS保持关断状态。 这可以防止由于高电流流过有源或使用的输出逆变器串造成的任何损坏。

公开(公告)号：US06730968B1

公开(公告)日：2004-05-04

申请号：US10205520

申请日：2002-07-25

Applicant: Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L2362

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ESD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract translation: 本发明提供了用于整个芯片静电放电，ESD保护方案的两个电路实施例。 它还包括一种全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06653709B2

公开(公告)日：2003-11-25

申请号：US10213612

申请日：2002-08-07

Applicant: Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

Inventor： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

IPC: H01L2972

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L27/0266

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

公开(公告)号：US06614078B2

公开(公告)日：2003-09-02

申请号：US10147272

申请日：2002-05-16

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

IPC: H01L2976

CPC classification number: H01L21/823878 ,  H01L27/0921

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

公开(公告)号：US06479872B1

公开(公告)日：2002-11-12

申请号：US09221959

申请日：1998-12-28

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

Abstract translation: 描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。 动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。 门控MOS晶体管具有连接到电接触焊盘的漏极区域。 栅极和源极连接到电源电压源。 电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。 电源电压源将是门控PMOS晶体管的电源电压源VDD。 电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。 电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。