Production flow and reusable testing method
    142.
    发明授权
    Production flow and reusable testing method 有权
    生产流程和可重复使用的检测方法

    公开(公告)号:US08614105B2

    公开(公告)日:2013-12-24

    申请号:US13247071

    申请日:2011-09-28

    IPC分类号: H01L21/66

    摘要: An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card.

    摘要翻译: 实施例是一种方法。 该方法包括提供包括管芯区域的衬底。 管芯区域包括焊盘图案的部分,并且这些部分的第一部分各自包括第一均匀焊盘图案。 该方法还包括用第一探针卡探测第一部分中的第一部分; 将第一探针卡推到第一部分的第二部分; 并用第一个探针卡探测第一个部分的第二个部分。

    Reordering in the memory controller
    143.
    发明授权
    Reordering in the memory controller 有权
    在内存控制器中重新排序

    公开(公告)号:US08510521B2

    公开(公告)日:2013-08-13

    申请号:US12883888

    申请日:2010-09-16

    IPC分类号: G06F12/00

    CPC分类号: G06F13/1642 G06F13/1626

    摘要: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

    摘要翻译: 在一个实施例中,存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中,可以为业务类型定义服务质量(QoS)参数,并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中,当接收到具有较高QoS参数,经由边带请求和/或通过操作老化的后续操作时,存储器控制器可以支持QoS参数的升级。 在一个实施例中,存储器控制器被配置为当操作流过存储器控制器管线时,减少对QoS参数的强调并且增加对存储器带宽优化的重视。

    Cellular authentication for authentication to a service
    145.
    发明授权
    Cellular authentication for authentication to a service 有权
    用于认证到服务的蜂窝认证

    公开(公告)号:US08442527B1

    公开(公告)日:2013-05-14

    申请号:US12358324

    申请日:2009-01-23

    摘要: An identification system comprises a communication interface. The communication interface is configured to receive from a mobile device a registration request to initiate an access session between the mobile device and a communication network, wherein the registration request comprises a device identifier that identifies the mobile device. In response to the registration request, the communication interface is configured to transfer a packet address to the mobile device, wherein the mobile device transfers a service request for a service on the communication network during the access session, wherein the service request includes the packet address. The communication interface is configured to receive an identification request transferred from an authentication system in response to the service request, wherein the identification request indicates the packet address. In response to the identification request, the communication interface is configured to transfer the device identifier for delivery to the authentication system to authenticate the mobile device for the service using the device identifier.

    摘要翻译: 识别系统包括通信接口。 通信接口被配置为从移动设备接收登记请求以发起移动设备和通信网络之间的接入会话,其中该注册请求包括识别该移动设备的设备标识符。 响应于所述注册请求,所述通信接口被配置为将分组地址传送到所述移动设备,其中所述移动设备在所述访问会话期间在所述通信网络上传送对服务的服务请求,其中所述服务请求包括所述分组地址 。 通信接口被配置为响应于服务请求接收从认证系统传送的标识请求,其中标识请求指示分组地址。 响应于所述识别请求,所述通信接口被配置为将所述设备标识符传送到所述认证系统,以使用所述设备标识符认证所述服务的所述移动设备。

    TOLVAPTAN SOLID DISPERSION AND ITS PREPARATION METHOD
    146.
    发明申请
    TOLVAPTAN SOLID DISPERSION AND ITS PREPARATION METHOD 有权
    TOLVAPTAN固体分散体及其制备方法

    公开(公告)号:US20130102588A1

    公开(公告)日:2013-04-25

    申请号:US13806173

    申请日:2011-06-02

    IPC分类号: A61K47/32 A61K9/10 A61K31/55

    摘要: A tolvaptan solid dispersion and its preparation method are disclosed. The solid dispersion comprises tolvaptan and cross-linked polyvinylprrolidone at a weight ratio of 1:0.05-20, preferably 1:0.1-10, and more preferably 2:1. The solid dispersion can further comprise one or more water-soluble polymers, such as polyvinylprrolidone, hydroxypropyl cellulose, hydroxyethyl cellulose or methylcellulose, wherein the weight ratio of tolvaptan:the crosslinked polyvinylprrolidone:the water-soluble polymers is preferably 2:1:0.1. The solid dispersion exhibits good thermodynamic stability and solubility. The pharmaceutical composition thereof has improved release rate and bioavailability.

    摘要翻译: 披露托伐普坦固体分散体及其制备方法。 固体分散体包含托伐普坦和交联聚乙烯吡咯烷酮,重量比为1:0.05-20,优选为1:0.1-10,更优选为2:1。 固体分散体可以进一步包含一种或多种水溶性聚合物,如聚乙烯吡咯烷酮,羟丙基纤维素,羟乙基纤维素或甲基纤维素,其中托伐普坦:交联聚乙烯吡咯烷酮:水溶性聚合物的重量比优选为2:1:0.1。 固体分散体表现出良好的热力学稳定性和溶解性。 其药物组合物具有改善的释放速率和生物利用度。

    3D IC Testing Apparatus
    147.
    发明申请
    3D IC Testing Apparatus 有权
    3D IC测试仪器

    公开(公告)号:US20120286814A1

    公开(公告)日:2012-11-15

    申请号:US13105603

    申请日:2011-05-11

    IPC分类号: G01R31/20 H01L21/66

    摘要: A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once.

    摘要翻译: 三维(3D)集成电路(IC)测试装置包括多个连接装置。 当由测试模式操作诸如由多个3D裸片形成的插入器或3D IC的受测设备(DUT)时,3D IC测试装置经由诸如探针的各种接口通道耦合到DUT。 DUT中的连接装置和各种通孔通孔(TSV)形成一个TSV链,以便可以一次性地测试各种TSV的电特性测试。

    Adaptive Test Sequence for Testing Integrated Circuits
    148.
    发明申请
    Adaptive Test Sequence for Testing Integrated Circuits 有权
    用于测试集成电路的自适应测试序列

    公开(公告)号:US20120246514A1

    公开(公告)日:2012-09-27

    申请号:US13072325

    申请日:2011-03-25

    IPC分类号: G06F11/07

    摘要: A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence.

    摘要翻译: 一种方法包括测试彼此相同并包括集成电路的第一设备和第二设备。 根据第一装置的第一测试顺序执行第一装置的测试,其中第一测试序列包括多个有序测试项目,并且其中第一测试序列包括测试项目。 基于与第一装置具有相同结构的多个装置的测试中的测试项目的失败频率来计算测试项目的测试优先级。 然后调整第一测试序列以响应于测试项目的测试优先级产生第二测试序列,其中第二测试序列与第一测试序列不同。 根据第二个测试顺序对第二个设备进行测试。

    Mechanism for Updating Memory Controller Timing Parameters During a Frequency Change
    149.
    发明申请
    Mechanism for Updating Memory Controller Timing Parameters During a Frequency Change 审中-公开
    更新频率内存控制器时序参数的机制

    公开(公告)号:US20120159230A1

    公开(公告)日:2012-06-21

    申请号:US12972033

    申请日:2010-12-17

    申请人: Hao Chen

    发明人: Hao Chen

    IPC分类号: G06F1/04 G06F12/00

    摘要: A mechanism for updating memory controller timing parameters during a frequency change includes a memory controller that controls memory transactions to a memory unit. The integrated circuit may also include a power manager unit that is coupled to the memory controller and may be configured to provide an indication that a memory clock frequency is changing to a new frequency. The integrated circuit also includes a storage that includes a number of entries. Each entry may store a predetermined set of timing values that corresponds to a respective memory clock frequency. In response to receiving the indication, the memory controller may access a given entry of the storage that corresponds to the new frequency, and may generate new timing values that correspond to the new frequency based upon the predetermined set of timing values stored within the given entry.

    摘要翻译: 用于在频率变化期间更新存储器控制器定时参数的机构包括控制到存储器单元的存储器事务的存储器控​​制器。 集成电路还可以包括功率管理器单元,其耦合到存储器控制器,并且可以被配置为提供存储器时钟频率正在改变到新的频率的指示。 集成电路还包括包括多个条目的存储器。 每个条目可以存储对应于相应存储器时钟频率的预定定时值组。 响应于接收到指示,存储器控制器可以访问对应于新频率的存储器的给定条目,并且可以基于存储在给定条目中的预定定时值集合来生成对应于新频率的新定时值 。